Air-Gap Spacers Reduce Parasitic Capacitance in Non-Planar FETs
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Solution Overview
Problem
Non-planar FET architectures, such as FinFETs, face high parasitic capacitance issues due to gate spacers, which degrade electrical performance by inducing RC time delay, especially as integrated chip components shrink in size.
Innovation Solution
The introduction of air-gap spacers with encapsulated bottom air-gaps positioned between the gate and source/drain regions, and potentially above the channel fin, reduces parasitic capacitance by utilizing a low-dielectric material like SiOCN, which has a lower dielectric constant than conventional materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional gate spacers are used in non-planar FET architectures, then device density and performance are improved, but parasitic capacitance increases causing RC time delay
Solution Approach 1:
The patent changes the dielectric parameter of the gate spacer material from conventional high-k materials to low-k materials (k<2.5, preferably k<2.0), which directly reduces the parasitic capacitance between the gate and source/drain regions while maintaining the spacer's structural function for device density
Solution Approach 2:
The patent introduces an intermediary air-gap structure within the gate spacer, creating a low-dielectric-constant region that mediates between the gate and source/drain regions. This air-gap acts as a capacitor with minimal capacitance, reducing the harmful parasitic effect while the spacer material maintains the lateral spacing function
2Area of stationary object
If gate spacers are positioned close to source/drain regions, then lateral space is optimized, but parasitic capacitance increases
Solution Approach 1:
The patent changes the dielectric parameter of the gate spacer material from conventional high-k materials to low-k materials (k<2.5, preferably k<2.0), which directly reduces the parasitic capacitance between the gate and source/drain regions while maintaining the spacer's structural function for device density
Solution Approach 2:
The patent introduces an intermediary air-gap structure within the gate spacer, creating a low-dielectric-constant region that mediates between the gate and source/drain regions. This air-gap acts as a capacitor with minimal capacitance, reducing the harmful parasitic effect while the spacer material maintains the lateral spacing function
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance, enhancing electrical performance by minimizing dielectric constant differences between the gate and source/drain regions, thereby improving control over channel current flow and reducing RC time delays.
Implementation Method 1
reduces parasitic capacitance by utilizing a low-dielectric material like SiOCN, which has a lower dielectric constant than conventional materials
Data Source
AI summary
Embodiments of the invention are directed to a method of fabricating a field effect transistor device, wherein the fabrication operations include forming a channel region over a substrate, forming a gate region over a top surface and along sidewalls of the channel region, and forming a source or drain (S/D) region over the substrate. A bottom encapsulated air-gap is formed over the substrate, and a first portion of the bottom encapsulated air-gap is positioned between the gate region and the S/D region. The first portion of the bottom encapsulated air-gap is further positioned below the top surface of the channel region.