Air Gap TSV Structure for Parasitic Capacitance Reduction

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In 3D integration technology, the parasitic capacitance of through silicon via (TSV) electrodes impacts the electrical characteristics of semiconductor devices, necessitating a reduction in parasitic capacitance to enhance performance.

Innovation Solution

A method involving the formation of a precursor structure with a conductor surrounded by an air gap, clamped by redistribution layers, which reduces parasitic capacitance by isolating the conductor from the substrate and surrounding elements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a through silicon via (TSV) electrode is formed to interconnect conductive pads, then electrical connections between conductive pads are established, but parasitic capacitance increases and electrical characteristics deteriorate

Engineering Contradiction:
Improveelectrical characteristicsVSAvoidparasitic capacitance
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent introduces an air gap structure surrounding the TSV electrode, effectively creating a porous/void space that reduces dielectric material around the conductor. This air gap has significantly lower permittivity compared to conventional dielectric materials, thereby reducing parasitic capacitance while maintaining electrical connection functionality between conductive pads

Inventive Principle:
Principle #31Porous materials

Solution Approach 2:

The patent employs a composite structure combining conductor material (copper or other conductive material), liner material (adhesion barrier), and air gap (void space). This composite approach optimizes electrical conductivity while minimizing parasitic capacitance through the strategic use of low-permittivity air space surrounding the TSV electrode

Inventive Principle:
Principle #40Composite materials

2Reliability

If the conductor is surrounded by dielectric material for insulation, then electrical isolation is achieved, but parasitic capacitance and leakage current increase

Engineering Contradiction:
Improveelectrical isolationVSAvoidleakage current
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The air gap structure serves as an insulating medium with extremely low permittivity, providing electrical isolation while minimizing parasitic capacitance and leakage current paths between adjacent conductive structures

Inventive Principle:
Principle #31Porous materials

Solution Approach 2:

The air gap creates an inert void environment around the TSV electrode, eliminating dielectric material that would otherwise create leakage current paths and parasitic capacitance, while the liner material maintains adhesion and prevents short circuits

Inventive Principle:
Principle #39Inert atmosphere (Inert environment)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The air gap significantly reduces parasitic capacitance and leakage current density, improving the overall electrical performance of semiconductor devices.

Implementation Method 1

the existence of the TSV parasitic capacitance is a key to impact the electrical characteristic. Thus, further improvements are needed to reduce the parasitic capacitance and enhance performance of semiconductor device

Methodology Applied
Scientific EffectParasitic capacitance reduction: Capacitance

Implementation Method 2

The air gap significantly reduces parasitic capacitance and leakage current density, improving the overall electrical performance of semiconductor devices

Methodology Applied
Scientific EffectLeakage current reduction: Electrical Resistance

Data Source

PatentUS10896848B1Method of manufacturing a semiconductor device
Publication Date: 2021.01.19 NAN YA TECH
  • US10896848B1 patent drawing
  • US10896848B1 patent drawing
  • US10896848B1 patent drawing

AI summary

A method of manufacturing a semiconductor device includes forming a precursor structure including a substrate having a via hole, a liner on a sidewall of the via hole, a conductor in the via hole, a first and a second insulating layers respectively on the top and bottom surfaces, and a first and a second redistribution layers in contact with the conductor through a first hole in the first insulating layer and a second hole in the second insulating layer. A first opening and a second opening are then respectively formed in the first insulating layer and the second insulating layer to expose a portion of the liner. The liner is then etched through the first opening and the second opening to form an air gap surrounding the conductor. The first opening and the second opening are then filled to seal the air gap.