3D Non-Volatile Memory Air Gap Word Line Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional three-dimensional non-volatile memory devices face limitations in program speed due to excessively high capacitance between word lines, which is caused by the interlayer insulating oxide layer.
Innovation Solution
The introduction of air gaps in the interlayer insulating layers between word line conductive layers, achieved through a manufacturing process involving the alternation of sacrificial layers and etching to form vertical channels and slits, reduces capacitance and enhances program speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an oxide layer is used as the interlayer insulating layer between memory cells, then the structure provides electrical insulation, but the capacitance between word lines becomes excessively high, increasing program time
Solution Approach 1:
The patent changes the dielectric parameter of the interlayer insulating layer from oxide (high dielectric constant) to air gap (zero dielectric constant). This parameter change reduces the capacitance between word lines from C=εoxA/d to C=0, directly addressing the high capacitance issue that causes long program times while maintaining electrical insulation functionality
Solution Approach 2:
The patent extracts the air gap from the interlayer insulating layer structure, creating a void space between the oxide layers. This extraction removes the harmful dielectric material that contributes to high capacitance, allowing the structure to maintain insulation through the oxide layers while the air gap provides the low-capacitance environment needed for fast programming
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The formation of air gaps in the interlayer insulating layers significantly reduces capacitance between word lines, thereby improving the program speed of memory cells in three-dimensional non-volatile memory devices.
Implementation Method 1
an air gap formed in the plurality of interlayer insulating layers disposed between the plurality of memory cells
Data Source
AI summary
A three-dimensional (3-D) non-volatile memory device includes a plurality of vertical channel layers protruding from a substrate, a plurality of interlayer insulating layers and a plurality of memory cells stacked alternately along the plurality of vertical channel layers, and an air gap formed in the plurality of interlayer insulating layers disposed between the plurality of memory cells, so that capacitance between word lines is reduced to thus improve a program speed.