Air Gaps Between Conductive Structures Reduce Parasitic Capacitance
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Solution Overview
Problem
As semiconductor devices become more integrated, the increasing parasitic capacitance between conductive structures due to reduced gaps and high dielectric constants of materials like silicon oxide and silicon nitride hinders operation speed and refresh characteristics, while increasing gaps or reducing structure heights is limited by size and resistance constraints.
Innovation Solution
The introduction of air gaps between conductive structures, achieved by forming multi-layered dielectric patterns with a low dielectric constant material like boron nitride, reduces parasitic capacitance by creating empty spaces with a dielectric constant of 1, thereby minimizing capacitance without increasing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the gap between conductive structures is increased to reduce parasitic capacitance, then parasitic capacitance is reduced, but device size increases and integration degree decreases
Solution Approach 1:
The patent applies local quality by introducing air gaps specifically at critical interfaces between conductive structures where parasitic capacitance is most problematic, rather than uniformly increasing gaps throughout the device. This targeted approach reduces parasitic capacitance at key locations without proportionally increasing overall device area.
Solution Approach 2:
The patent introduces air gaps (essentially porous spaces filled with air having dielectric constant of 1) between conductive structures. These air gaps act as low-dielectric constant regions that reduce parasitic capacitance while occupying minimal space compared to solid dielectric materials.
2Object-affected harmful factors
If the height of conductive structures is decreased to reduce facing area and parasitic capacitance, then parasitic capacitance is reduced, but resistance increases
Solution Approach 1:
The patent applies local quality by introducing air gaps specifically at interfaces between conductive structures where parasitic capacitance is most problematic, rather than uniformly increasing gaps throughout the device. This targeted approach reduces parasitic capacitance at key locations without proportionally increasing overall device area.
Solution Approach 2:
The patent introduces air gaps (essentially porous spaces filled with air having dielectric constant of 1) between conductive structures. These air gaps act as low-dielectric constant regions that reduce parasitic capacitance while occupying minimal space compared to solid dielectric materials.
3Ease of manufacture
If conventional dielectric materials like silicon oxide or silicon nitride are used, then manufacturing is straightforward, but parasitic capacitance remains high due to high dielectric constants
Solution Approach 1:
The patent introduces air gaps (essentially porous spaces filled with air having dielectric constant of 1) between conductive structures. These air gaps act as low-dielectric constant regions that reduce parasitic capacitance while occupying minimal space compared to solid dielectric materials.
Solution Approach 2:
The patent creates a composite structure combining conventional dielectric materials with air gaps. This composite approach maintains the manufacturability of standard dielectric processes while incorporating low-dielectric constant air regions to reduce overall parasitic capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance between conductive structures, enhancing operation speed and refresh characteristics while maintaining integration density without significant increases in resistance or material complexity.
Implementation Method 1
The introduction of air gaps between conductive structures, achieved by forming multi-layered dielectric patterns with a low dielectric constant material like boron nitride, reduces parasitic capacitance by creating empty spaces with a dielectric constant of 1
Data Source
AI summary
A method for fabricating a semiconductor device includes forming, over a substrate, a plurality of first conductive structures which are separated from one another; forming multi-layered dielectric patterns including a first dielectric layer which covers upper ends and both sidewalls of the first conductive structures; removing portions of the first dielectric layer starting from lower end portions of the first conductive structures to define air gaps, and forming second conductive structures which are filled between the first conductive structures.