Airgap Spacer and Backside Contact Layout for Nanosheet Routing
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Solution Overview
Problem
Current integrated circuit fabrication methods face challenges in reducing parasitic capacitance and ensuring flexible routing while avoiding short circuits in three-dimensional transistor structures, particularly in nanosheet transistors with airgap spacers and direct backside contacts.
Innovation Solution
The method involves forming an airgap spacer on one side of the transistor and a solid spacer on the other, with the source/drain epitaxial region adjacent to the airgap spacer connected to the frontside and the solid spacer connected to the backside, allowing for a local interconnect that can fly over the backside contact for flexible routing and avoiding potential short circuits by using a solid spacer instead of an airgap.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If an airgap spacer is used on both sides of the transistor, then parasitic capacitance is reduced, but the risk of short circuits between backside contact and gate increases
Solution Approach 1:
The patent applies different spacer configurations to different sides of the transistor: an airgap spacer is used on the frontside to reduce parasitic capacitance, while a solid spacer is used on the backside to prevent short circuits. This local differentiation allows each side to optimize for its specific functional requirements without compromising overall device reliability.
2Reliability
If a solid spacer is used instead of airgap spacer, then short circuit risk is eliminated, but parasitic capacitance increases
Solution Approach 1:
The patent applies different spacer configurations to different sides of the transistor: an airgap spacer is used on the frontside to reduce parasitic capacitance, while a solid spacer is used on the backside to prevent short circuits. This local differentiation allows each side to optimize for its specific functional requirements without compromising overall device reliability.
3Area of stationary object
If airgap spacers are used, then space is consumed, but routing flexibility is limited due to short circuit risks
Solution Approach 1:
The patent applies different spacer configurations to different sides of the transistor: an airgap spacer is used on the frontside to reduce parasitic capacitance, while a solid spacer is used on the backside to prevent short circuits. This local differentiation allows each side to optimize for its specific functional requirements without compromising overall device reliability.
Solution Approach 2:
The patent utilizes the backside of the transistor as an additional dimension for interconnect routing. By forming backside contacts and routing interconnects through the backside, the design gains additional routing paths that can bypass frontside congestion without introducing short circuit risks, thereby improving routing flexibility.
4Adaptability or versatility
If direct backside contact is implemented, then routing flexibility improves, but the risk of short circuits with gate increases
Solution Approach 1:
The patent applies different spacer configurations to different sides of the transistor: an airgap spacer is used on the frontside to reduce parasitic capacitance, while a solid spacer is used on the backside to prevent short circuits. This local differentiation allows each side to optimize for its specific functional requirements without compromising overall device reliability.
Data Source
AI summary
Embodiments of the invention include a transistor having a first source/drain region and a second source/drain region on opposite sides of the transistor, the first source/drain region being below an airgap spacer and electrically connected to a front side of the transistor, the second source/drain region being adjacent to a solid spacer and electrically connected to a backside of the transistor. The front side is above the transistor, and the backside is below the transistor