3D Memory Airgap Insulating Layers for Low-k Dielectric
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in efficiently integrating airgap-containing insulating layers to enhance insulation and reduce dielectric constant, which is crucial for improving memory device performance and scalability.
Innovation Solution
A method of forming a three-dimensional memory device by creating a vertical repetition of unit layer stacks comprising an airgap-containing insulating layer, a first interfacial dielectric capping layer, a metal layer, and a second interfacial dielectric capping layer, where the sacrificial material layer is replaced with an insulating layer, and memory stack structures are formed with vertical semiconductor channels and memory elements at metal layer levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional insulating layers are used in vertical NAND strings, then the structure is simpler to manufacture, but the dielectric constant remains high which limits memory device performance and scalability
Solution Approach 1:
The patent uses composite insulating layers combining low-k dielectric material and airgap regions. The airgap-containing insulating layer is formed by depositing a low-k dielectric material over sacrificial material, then selectively removing the sacrificial material to create airgaps. This composite structure achieves lower effective dielectric constant while maintaining manufacturability through established deposition and etch processes.
Solution Approach 2:
The airgap-containing insulating layer introduces porosity into the insulating structure by creating airgaps between memory stack structures. These airgaps reduce the effective dielectric constant of the insulating layer, improving memory device performance. The porous structure is formed through selective removal of sacrificial material followed by dielectric material deposition.
2Reliability
If airgap-containing insulating layers are integrated to reduce dielectric constant, then memory device performance improves, but the manufacturing process becomes more complex
Solution Approach 1:
The sacrificial material layer is deposited and patterned before forming the low-k dielectric material. This preliminary action creates a template that guides the subsequent formation of airgaps. The sacrificial material serves as a placeholder that is later removed to create the desired airgap structure, simplifying the overall manufacturing process by pre-defining the airgap locations.
Solution Approach 2:
The sacrificial material acts as an intermediary element during manufacturing. It is temporarily introduced to define the airgap structure, then removed after serving its purpose. This intermediary approach allows complex airgap-containing insulating layers to be formed using standard deposition and etch processes, rather than requiring novel manufacturing techniques.
3Reliability
If airgaps are created by removing sacrificial material, then insulation is improved, but additional manufacturing steps are required
Solution Approach 1:
The formation of airgaps is merged with the existing sacrificial material removal step in the vertical NAND manufacturing process. Instead of adding a separate airgap creation step, the process combines dielectric material deposition over sacrificial material with the subsequent sacrificial material removal that already occurs in the manufacturing flow. This merging approach improves insulation without significantly impacting manufacturing efficiency.
Solution Approach 2:
The sacrificial material removal step serves multiple functions: it defines the airgap structure for reduced dielectric constant, and it also prepares the surface for subsequent dielectric material deposition. This multi-functionality allows the manufacturing process to create airgap-containing insulating layers using existing process steps, thereby improving insulation quality while maintaining manufacturing efficiency.
Data Source
AI summary
A three-dimensional memory device includes a vertical repetition of multiple instances of a unit layer stack. The unit layer stack includes, in order, an airgap-containing insulating layer, a first interfacial dielectric capping layer, a metal layer, and a second interfacial dielectric capping layer. Memory stack structures extend through the vertical repetition. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of memory elements located at levels of the metal layers.