ALD Via Structure for Seamless Magnetoresistive Stack Interconnects
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Solution Overview
Problem
The challenge in the field of magnetoresistive devices is the difficulty in effectively fabricating small vias, particularly those with diameters less than 100 nm, which is necessary for higher density memory components, as conventional methods often result in seams and compromised electrical conductivity and structural integrity.
Innovation Solution
The use of atomic layer deposition (ALD) to form 'on-axis' vias by depositing transition metal layers and tantalum-rich layers within trenches, allowing for seamless integration of magnetoresistive stacks between metal layers, thereby ensuring bidirectional current transfer and improved electrical and structural performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods are used to fabricate small vias, then manufacturing process simplicity is maintained, but via structural integrity and electrical conductivity deteriorate due to seams
Solution Approach 1:
The via fabrication is divided into multiple sequential deposition steps (first transition metal layer, second transition metal layer, tantalum-rich layer) rather than attempting to form the complete via in a single step. This segmentation allows each layer to be optimized for specific functions, eliminating seams and improving structural integrity while maintaining manufacturing feasibility through standardized ALD processes.
Solution Approach 2:
The method performs preliminary actions by depositing multiple preparatory layers (transition metal layers followed by tantalum-rich layer) before final via completion. These preliminary layers serve as foundations that prevent seam formation and ensure proper electrical conductivity, addressing reliability issues before the via fabrication is finalized.
2Productivity
If via diameter is reduced to increase memory density, then memory component density improves, but manufacturing difficulty and via quality deteriorate
Solution Approach 1:
The invention changes material parameters by using different transition metals (cobalt, ruthenium, copper, aluminum) and controlling their thicknesses (5-50 nm ranges) to achieve precise via dimensions. The multi-layer approach with specific thickness parameters enables sub-100 nm via fabrication with high precision, supporting increased memory density while maintaining manufacturing quality.
Solution Approach 2:
The via structure uses composite materials comprising multiple transition metal layers and a tantalum-rich layer, each contributing different properties. This composite structure enables precise control of via dimensions and properties at sub-100 nm scales, achieving both high memory density and manufacturing precision through material composition optimization.
3Reliability
If multi-layer via structure is implemented to eliminate seams, then electrical conductivity improves, but manufacturing process complexity increases
Solution Approach 1:
The atomic layer deposition process serves multiple functions simultaneously: it deposits transition metal layers, deposits tantalum-rich layers, controls layer thicknesses, and ensures uniform coverage throughout the via structure. This universal ALD approach achieves seamless via formation and improved electrical conductivity while keeping the manufacturing process manageable through a single versatile deposition technique.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of vias without seams, enhancing the electrical conductivity and structural integrity of magnetoresistive devices, facilitating the integration of smaller magnetoresistive stacks for higher density memory applications.
Implementation Method 1
An exemplary magnetoresistive stack (for example, one using a magnetic tunnel junction (MTJ)) of the present disclosure may be integrated with other exemplary magnetoresistive stacks through the use of a via comprising one or more layers deposited by atomic layer deposition (ALD)
Data Source
Figure 1A~1C
Figure 2A~2C
Figure 2D~3B
AI summary
Fabrication of a magnetic memory element, including a via (125) in an interlevel dielectric layer (120), providing an electrical connection between an underlying metal region (110) and a magnetoresistive stack device, such as a magnetic tunnel junction (150), involves forming a transition metal layer (130) in the via by atomic layer deposition. The via optionally includes a tantalum-rich layer (140) above, and/or a cap layer (115) below, the transition metal layer, and may have a diameter less than or equal than a diameter of the magnetoresistive stack device.