Semiconductor Alignment Mark Structure for Stronger Diffracted Light
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Solution Overview
Problem
The intensity of diffracted light for alignment marks in semiconductor structures is low, leading to poor accuracy in identifying alignment marks, which affects the measurement and compensation of overlay (OVL) during the manufacturing process.
Innovation Solution
A method involving the formation of a layer stack on a substrate with a first conductive layer as the bottom layer, followed by etching to create first and second trenches in the device and alignment regions, respectively, where the second trenches form alignment marks, enhancing the intensity of diffracted light and improving alignment accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If light beams are used for detecting alignment marks, then alignment detection can be performed, but the intensity of diffracted light is low leading to poor identification accuracy
Solution Approach 1:
The patent applies the color changes principle by utilizing the first conductive layer's ability to interact with light in specific ways. The conductive layer, made of polysilicon or doped polysilicon, has optical properties that enhance light diffraction and reflection when light beams pass through or reflect off the alignment marks formed in the layer stack, thereby increasing the intensity of diffracted light reaching the image sensor and improving alignment mark identification accuracy
Solution Approach 2:
The patent employs composite materials by creating a layer stack that includes multiple layers with different material properties. The first conductive layer (polysilicon or doped polysilicon) is combined with other dielectric and conductive layers to form a composite structure. This composite layer stack enhances the optical interaction with incident light beams, producing stronger diffraction patterns and improving the intensity and quality of light signals used for alignment mark detection
2Ease of manufacture
If the first conductive layer is removed in the alignment region to form alignment marks, then alignment marks can be formed, but the manufacturing process becomes more complex
Solution Approach 1:
The patent applies the merging principle by combining the alignment mark formation process with the existing conductive layer structure. Instead of removing the first conductive layer to create alignment marks, the invention retains the layer stack structure intact and forms alignment marks by etching trenches through the entire layer stack in the alignment region. This merging of the conductive layer with the alignment mark structure simplifies the manufacturing process by eliminating separate removal steps while still achieving functional alignment marks
Solution Approach 2:
The patent employs universality by making the layer stack serve multiple functions simultaneously. The first conductive layer, originally intended only for electrical conduction in the device region, is retained in the alignment region and serves dual purposes: maintaining electrical functionality and providing structural support for alignment mark formation. The layer stack becomes a multi-functional component that contributes to both device operation and alignment detection, thereby simplifying the overall manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances the intensity of diffracted light and improves the accuracy of alignment mark identification, resulting in better measurement and compensation of overlay, with reduced and stable ROPI values.
Implementation Method 1
The light beams diffract at the alignment marks. The diffracted light is imaged on an image sensor
Data Source
AI summary
Embodiments of the disclosure provide a semiconductor structure and a method for manufacturing the same. The method includes the following operations. A substrate is provided, in which the substrate includes a device region and an alignment region. A layer stack covering the device region and the alignment region is formed on the substrate, in which the layer stack at least includes a first conductive layer as a bottom layer of the layer stack, and a material of the first conductive layer includes a semiconductor material. The layer stack is etched to respectively form first trenches in the device region and second trenches in the alignment region which penetrate through the layer stack, in which the second trenches and the layer stack located between the second trenches form alignment marks.