3D Wafer Integration via Alignment Via Bonding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current 3D wafer stacking technologies face challenges with temporary adhesives that limit in-fab processing and raise reliability concerns due to thermal instability, and achieving accurate alignment of pre-existing through substrate vias across wafer diameters is difficult, leading to alignment issues.
Innovation Solution
The method involves forming deep through substrate vias post-bonding using a prebuilt alignment via as an alignment mark, allowing for non-via bonding such as oxide-to-oxide bonding, which eliminates alignment issues and reduces the need for temporary adhesives, enabling more precise and reliable 3D wafer integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If pre-existing through substrate vias are used for alignment, then alignment is simplified, but alignment accuracy deteriorates due to difficulty in achieving accurate alignment across wafer diameters
Solution Approach 1:
Alignment vias are formed in the first substrate before bonding to the second substrate. These pre-formed alignment vias serve as reference markers that enable accurate alignment during the bonding process, eliminating the need for complex post-bonding alignment operations while maintaining high alignment precision across the wafer diameter
Solution Approach 2:
The alignment vias act as intermediary reference structures between the first and second substrates. By providing physical alignment markers that can be optically detected, they mediate the alignment process between two separate substrates, enabling precise positioning without requiring complex mechanical alignment systems
2Ease of manufacture
If temporary adhesives are used for wafer bonding, then bonding process is simplified, but reliability deteriorates due to thermal instability limiting in-fab processing
Solution Approach 1:
The patent extracts and eliminates the temporary adhesive layer from the bonding process by implementing alignment via bonding. The alignment vias are filled with conductive material that provides both structural support and electrical connection, removing the need for separate temporary adhesive materials that have thermal instability issues
Solution Approach 2:
The bonding process transitions from using organic temporary adhesives with low thermal stability to using inorganic conductive materials (such as copper or tungsten) filled in alignment vias. This parameter change in material composition dramatically improves thermal stability, enabling the bonded structure to withstand subsequent high-temperature fabrication processes
Data Source
AI summary
A method includes forming a first integrated circuit (IC) device having a first substrate, an alignment via defined in the first substrate, a first wiring layer over the alignment via, and a first bonding layer over the first wiring layer; forming a second IC device having a second substrate, a second wiring layer over the second substrate, and a second bonding layer over the second wiring layer; bonding the first bonding layer of first IC device to the second bonding layer of second IC device; thinning a backside of the first IC device so as to expose the alignment via; and using the exposed alignment via to form a deep, through substrate via (TSV) that passes through the first IC device, through a bonding interface between the first IC device and second IC device, and landing on the second wiring layer of the second IC device.