Solid-State Devices TRIZ Cases

Segmenting the insulating film into distinct silicon nitride and oxide layers resolves the trade-off between data retention and charge injection efficiency.

Convex encapsulation portions refract emitted light to increase beam angle, reducing total internal reflection that limits light extraction efficiency.

Switching transistors segment bit lines to reduce RC delay, enhancing operating speed in vertical NAND structures.

A double gate thin film transistor uses a metal layer connected to a transparent conductive oxide top gate electrode.

Adjacent layers of phase-change memory cells perform logic operations directly through reversible amorphous and crystalline phase transitions.

Pulsed microwave annealing prevents plastic substrate warpage during organic layer processing, improving device reliability and power conversion efficiency.

Transition metal layer generates heat in hydrogen plasma to form low-resistivity ohmic contacts on silicon carbide substrates.

Specific tilting angles and aspect ratios in truncated cone reflectors resolve luminance variations caused by manufacturing tolerances.

A nonvolatile memory device uses a block insulating layer to cover only the side surface of a charge accumulation layer, creating a thinner film region that suppresses charge migration.

Moving patterning slit sheets relative to substrates prevents mask distortion from self-gravity, enabling high-definition patterning on large-area displays.

An etch stop layer and buffer layer define photodiode depth in backside-illuminated image sensors.

Segmented insulating films and strategic contacts suppress potential differences under gate pads to prevent oxide film deterioration.

A low-refractive pattern fills spaces between color filters to refract incident light toward photodiodes.

Vias connect the metal shield to the substrate to remove accumulated charge, eliminating dark current and color mixing in backside illumination sensors.

Matching balanced composite structure coefficient of thermal expansion to alumina baseplate reduces detector array channel cracking and bowing.

A three-dimensional transition metal oxide data storage layer formed via chemical vapor deposition to achieve dense uniformity and precise oxygen content.

Alternating P+ and N+ doped regions in a universal contact diode enable soft reverse current recovery, reducing power loss and electromagnetic interference.

Dielectric-filled perforations in a patterned polysilicon layer create a graded refractive index that reduces reflection losses at the silicon interface.

Organic film coating on plastic substrates conducts heat during treatment to harden the surface, reducing deformation from thermal directivity in PEN materials.

Merging gate electrodes across adjacent PMOS and NMOS regions reduces routing area while maintaining independent signal control.

Connecting adjacent OLED cathodes via a dedicated wire reduces layer resistance, eliminating voltage drops that cause non-uniform light emission.

Organic-inorganic composite sacrificial layer withstands 400°C temperatures while absorbing laser energy to separate display substrates without damage.

Via holes in the color filter layer connect to insulated common lines, restoring signal continuity without photothermal damage to the display substrate.

Shared interconnects in merged n-well blocks supply split cells, resolving latch-up issues and manufacturing difficulties.

Dual-host layers convert triplet excitons via TADF, reducing expensive metal usage and roll-off in organic electroluminescent devices.

A solution-processed electroluminescent display uses a connection pattern with protrusions to form the light-emitting layer without a fine metal mask.

Orienting niobium oxide crystal planes in the stacking direction provides a low resistance initial state, eliminating time-consuming forming processing steps.

Continuous parallel extension of active regions prevents writing errors without isolation elements, reducing area per bit cell by 45%.

A pixel structure uses a photoresist and light-absorbing particle composite layer on conductive surfaces to block ambient light reflection.

A nanoscale vacuum electronic device structure enables thresholdless electron emission through Coulombic repulsion at the side wall interface.

Chemical mechanical polishing flattens the active area to enable thin metal deposition, eliminating voids in high aspect ratio gaps.

Stacked conductive layers form reservoir capacitors alongside transistor gates using shared deposition steps.

A carbon nanotube receives p-type doping through direct contact with a molybdenum disulfide or tungsten disulfide film.

A conductive paste joins electrodes to conductor tracks without high temperatures.

A buffer structure with graded lattice constants and rough surfaces reduces dislocation density and tensile stress to prevent cracking.

Segmented oxide-nitride support columns prevent stepped portion collapse, maintaining structural integrity and yield in 3D semiconductor memory.

A delta subpixel arrangement aligns red and green pixels along a column axis while positioning blue pixels in a zigzag row pattern.

Counting fail bits in partial page buffer columns reduces verification time while maintaining program reliability.

An asymmetric scavenger layer between bit and word lines confines conductive filament formation, resolving unpredictable switching in horizontal RRAM arrays.

Direct connections link block outputs to subsequent multiplier or adder inputs, reducing external routing resource usage during polynomial calculations.

Adjusting blue fluorescent dopant concentration matches luminance curves, stabilizing color coordinates across brightness levels.

In-situ steam generation consumes a patterned hard mask to form a gate oxide layer, preserving the ONO structure thickness ratio during fabrication.

Attachable handle portions on side faces of a radiographic image detection device facilitate portable handling.