Nonvolatile Memory Charge Accumulation Layer Thickness Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current nonvolatile semiconductor memory devices face challenges in increasing integration level and data storage characteristics, particularly in three-dimensional configurations, where charge migration and read failure rates are high due to the limitations in the structure and manufacturing processes of charge accumulation layers.
Innovation Solution
A nonvolatile semiconductor memory device is designed with a specific structure where a semiconductor layer has a tunnel insulating layer and a charge accumulation layer, with a block insulating layer covering only the side surface facing the conductive layer, and not the upper or lower surface, allowing for a thinner film thickness in one portion to suppress charge migration and improve data storage, while the block insulating layer's oxidation treatment enhances insulation and reduces resistance, enabling increased word line thickness for faster operation and reduced read failure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional charge accumulation layer structure is used in three-dimensional memory devices, then integration level can be increased, but charge migration occurs and read failure rate increases
Solution Approach 1:
The patent applies local quality by creating different thickness regions within the charge accumulation layer. The layer has a first region with a first thickness and a second region with a second thickness different from the first, allowing different functional characteristics in different locations to simultaneously achieve high integration and low read failure.
Solution Approach 2:
The patent transitions from a uniform two-dimensional charge accumulation layer to a three-dimensional structure with varying thickness. This dimensional change allows the charge accumulation layer to be positioned and sized differently in various regions, enabling better charge confinement and reduced migration while maintaining high integration density.
2Reliability
If the charge accumulation layer is made thinner to suppress charge migration, then read failure decreases, but data storage capacity is reduced
Solution Approach 1:
The patent uses local quality by having different thickness regions in the charge accumulation layer. The thinner second region suppresses charge migration and reduces read failure, while the thicker first region maintains data storage capacity, allowing both requirements to be satisfied simultaneously in different locations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses charge migration, improves data storage characteristics, reduces read failure, and enhances operation speed by optimizing the fringe electric field and channel formation, leading to improved performance in high-density memory devices.
Implementation Method 1
the block insulating layer's oxidation treatment enhances insulation and reduces resistance
Implementation Method 2
allowing for a thinner film thickness in one portion to suppress charge migration and improve data storage
Data Source
AI summary
According to an embodiment, a nonvolatile semiconductor memory device comprises a plurality of conductive layers stacked in a first direction via an inter-layer insulating layer. In addition, the nonvolatile semiconductor memory device comprises: a semiconductor layer having the first direction as a longer direction; a tunnel insulating layer contacting a side surface of the semiconductor layer; a charge accumulation layer contacting a side surface of the tunnel insulating layer; and a block insulating layer contacting a portion facing the conductive layer, of a side surface of the charge accumulation layer. Moreover, the portion facing the conductive layer, of the charge accumulation layer is thinner compared to a portion facing the inter-layer insulating layer, of the charge accumulation layer.