Non-volatile Memory Page Buffer Fail Bit Counting Optimization
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Solution Overview
Problem
Current non-volatile memory devices face challenges in improving program speed and fail bit counting performance, particularly in determining the success of programming operations in memory cells connected to a page buffer array.
Innovation Solution
The proposed solution involves an operating method for a non-volatile memory device with a page buffer array, where fail bits are counted in predetermined columns based on an operation mode, and a control logic determines the program success by comparing the count result with a reference count, allowing for the potential skipping of verification operations when the fail bit value is below a threshold.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If verification operations are performed for all memory cells after programming, then program reliability is improved, but program speed deteriorates
Solution Approach 1:
The patent applies partial verification by counting fail bits in only L columns (where L ≤ N) of the page buffer array instead of verifying all N columns. This partial action approach maintains acceptable reliability by sampling representative columns while significantly reducing the verification time and improving program speed.
Solution Approach 2:
The patent performs preliminary fail bit counting during the programming operation itself, before the final verification step. By counting fail bits in L columns during programming and comparing against a reference count, the system can determine program pass/fail status early, avoiding unnecessary complete verification operations and improving overall program speed.
2Measurement precision
If fail bits are counted in all columns of the page buffer array, then fail bit counting precision is improved, but device complexity increases
Solution Approach 1:
The patent counts fail bits in only L columns (where L ≤ N) of the page buffer array instead of all N columns. This partial counting approach maintains sufficient measurement precision for determining program pass/fail status while reducing the complexity of the counting circuitry and decreasing the number of operations required.
Solution Approach 2:
The patent changes the parameter of column sampling by selecting L columns out of N total columns based on the operation mode. This parameter adjustment allows the system to adapt the fail bit counting precision and complexity trade-off dynamically, optimizing performance for different operating conditions without requiring complex fixed circuitry.
3Measurement precision
If the number of columns for fail bit counting is increased, then fail bit detection accuracy is improved, but processing time increases
Solution Approach 1:
The patent performs partial fail bit counting in L columns instead of all N columns, achieving sufficient detection accuracy for program verification while significantly reducing the processing time required. This partial action approach prevents excessive time loss while maintaining adequate measurement precision.
Solution Approach 2:
The patent performs preliminary fail bit counting during the programming operation in L columns, establishing the fail bit count early in the process. This preliminary action reduces the overall processing time by avoiding subsequent complete verification counting, while still providing accurate enough information to determine program pass/fail status.
Data Source
AI summary
An operating method of a nonvolatile memory device including a page buffer array in which a plurality of page buffers are arranged in a matrix form includes counting fail bits stored in the page buffers included in first columns determined based on an operation mode from among a plurality of columns of the page buffer array, and determining whether or not a program has passed with respect to memory cells to which the page buffer array is connected, based on a count result corresponding to a number of the fail bits and a reference count determined based on the operation mode.