Bit Line Switches Reduce RC Delay in 3D Memory Arrays
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Solution Overview
Problem
The RC delay in bit lines of memory devices significantly contributes to the total sense time and programming time in three-dimensional memory devices, hindering their operating speed.
Innovation Solution
Incorporating bit line switches to reduce RC delay, these switches are integrated into three-dimensional memory devices with vertical NAND strings, allowing for improved operating speed by optimizing the bit line structure and connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If bit line switches are incorporated into three-dimensional memory devices, then operating speed is improved by reducing RC delay, but device complexity increases
Solution Approach 1:
The bit line is segmented into multiple portions (first bit line portion, second bit line portion) with switches positioned at intermediate locations. This segmentation allows selective activation of bit line segments, reducing the effective RC delay for accessed memory regions while maintaining the ability to access any region in the array.
Solution Approach 2:
Switches are pre-positioned at strategic locations along the bit lines (such as at boundaries between memory blocks or regions). These switches are activated in advance based on the access pattern, preparing the bit line configuration before the actual memory access occurs, thereby minimizing the RC delay during the critical access window.
2Loss of time
If bit line switches are added to reduce RC delay, then sense time and programming time are reduced, but manufacturing complexity increases
Solution Approach 1:
The switches are merged with the existing bit line structure and memory block organization. The switch control logic is integrated with the memory controller, allowing a single control signal to simultaneously manage multiple switches along the bit line, thereby reducing the number of independent control lines needed and simplifying the manufacturing process.
Solution Approach 2:
The bit line switches serve multiple functions: they act as selection switches for different memory regions, serve as isolation elements during erase operations, and provide control over signal propagation along the bit line. This multi-functionality reduces the need for separate dedicated structures for each function, simplifying overall device manufacturing.
Data Source
AI summary
A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.