Split N-Well Cells in Merged Blocks for Routing Congestion
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Solution Overview
Problem
The integration of split n-well cells into a merged n-well circuit block faces challenges such as area overhead, routing congestion, and latch-up issues due to the need for each split n-well cell to be routed to an always-on (AON) voltage source, making the design difficult or impossible to manufacture.
Innovation Solution
The solution involves a MOS device layout where split n-well cells are arranged with interconnects to share voltage sources efficiently, allowing continuous n-wells to be coupled to AON voltage sources through power pins, reducing routing congestion and enabling safe abutment with regular merged n-well cells, while maintaining power integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each split n-well cell is individually routed to an AON voltage source, then power integrity is maintained, but routing congestion increases and manufacturing becomes difficult
Solution Approach 1:
Multiple split n-well cells are merged into a single merged n-well block that shares a common AON voltage source connection. Instead of routing separate connections to each cell, the patent combines multiple cells into one block with unified power supply, eliminating routing congestion while maintaining power integrity for all cells in the block.
Solution Approach 2:
The merged n-well block serves multiple functions: it provides power supply to multiple split n-well cells simultaneously, maintains latch-up protection through the AON voltage source, and enables area-efficient packing of cells. This multi-functional approach resolves the contradiction by achieving power integrity for multiple cells through a single universal connection structure.
2Area of stationary object
If split n-well cells are integrated into merged n-well block, then area efficiency is improved, but routing congestion occurs due to multiple AON voltage source connections
Solution Approach 1:
The patent merges multiple split n-well cells into a single merged n-well block, reducing the total number of separate AON voltage source connections required. This consolidation maintains area efficiency while eliminating routing congestion by replacing multiple individual routes with a single shared connection path.
3Area of stationary object
If split n-well cells are placed adjacent to merged n-well cells, then area utilization is improved, but latch-up issues arise due to voltage level differences
Solution Approach 1:
The patent introduces an intermediary structure - the merged n-well block with AON voltage source - that mediates between split n-well cells and merged n-well cells. This intermediary maintains proper voltage levels and electrical isolation, preventing latch-up issues while allowing adjacent placement of different cell types for optimal area utilization.
Data Source
AI summary
In an aspect of the disclosure, a MOS device for reducing routing congestion caused by using split n-well cells (704) in a merged n-well circuit block (700) is provided. The MOS device includes a first set of cells (702) adjacent to each other in a first direction. The MOS device includes a second set of cells (704) adjacent to each other in the first direction and adjacent to the first set of cells in a second direction. The second set of cells each include a first n-well (712), a second n-well (714), and a third n-well (716) separated from each other. The MOS device includes an interconnect (720) extending in the first direction in the second set of cells (704). The interconnect (720) provides a voltage source to the first n-well (712) of each of the second set of cells (704).