Reservoir Capacitor Manufacturing via Shared Conductive Layers
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Solution Overview
Problem
Current semiconductor integrated circuit devices face challenges in manufacturing simple and effective reservoir capacitors, which are necessary for noise removal and signal transfer, especially in variable resistive memory devices like PCRAMs, due to the complexity of integrating capacitors with low voltage and high integration requirements.
Innovation Solution
A method of manufacturing a semiconductor integrated circuit device involves forming a stack structure of electrodes and dielectric layers to create a reservoir capacitor in one region and a gate in another, with specific etching and layering processes to achieve efficient capacitor formation without additional processes, allowing for improved signal transfer characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If reservoir capacitors are formed in peripheral regions of semiconductor integrated circuits, then noise removal capability is improved, but device complexity and manufacturing process complexity increase
Solution Approach 1:
The patent merges the reservoir capacitor formation process with the existing transistor gate formation process. By using the same conductive layers (first and second conductive layers) and dielectric layers for both the capacitor electrodes and the transistor gate, the manufacturing process complexity is reduced while maintaining noise removal capability. The shared layers are formed through common deposition and etching steps, eliminating the need for separate capacitor fabrication processes.
Solution Approach 2:
The conductive layers and dielectric layers are designed to serve multiple functions: they form both the reservoir capacitor electrodes in peripheral regions and the transistor gates in cell regions. This multi-functionality approach allows the same structural elements to provide both noise removal (through the capacitor) and device switching/control (through the gate), thereby reducing overall device complexity and manufacturing steps.
2Reliability
If additional manufacturing processes are used to form reservoir capacitors, then capacitor performance is improved, but manufacturing complexity and production time increase
Solution Approach 1:
The patent combines capacitor formation and gate formation into a single integrated manufacturing sequence. The first conductive layer, second conductive layer, and dielectric layers are deposited and patterned together for both capacitor and gate structures, eliminating the need for additional separate processes. This merging maintains capacitor performance through proper layer stacking while significantly improving manufacturing efficiency.
3Manufacturing precision
If multi-stage reservoir capacitors with large capacity are manufactured, then signal transfer characteristics are improved, but manufacturing complexity increases
Solution Approach 1:
The patent achieves large capacitor capacity through vertical stacking of multiple conductive and dielectric layers rather than expanding horizontal area. The multi-stage capacitor structure utilizes the third dimension (layer stacking) to increase capacitance while maintaining a compact footprint. This vertical integration approach improves signal transfer characteristics through adequate decoupling capacity without increasing manufacturing process complexity, as the stacked layers are formed through standard sequential deposition and etching processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the simultaneous manufacturing of a multi-stage reservoir capacitor with large capacity, enhancing signal transfer characteristics and reducing manufacturing complexity, thereby addressing the need for efficient noise removal in high integration, low voltage semiconductor devices.
Implementation Method 1
a reservoir capacitor formed in a first region and including a stack structure of a first electrode, a second electrode, a third electrode and dielectric layers, wherein the dielectric layers are interposed between the first and second electrodes and between the second and the third electrodes
Data Source
AI summary
A semiconductor integrated circuit device having a reservoir capacitor and a method of manufacturing the same are provided. A first insulating layer is formed on a semiconductor substrate including a first region and a second region. A first conductive layer is formed on the first insulating layer, and a second insulating layer is formed on the first conductive layer. The second insulating layer is patterned to be left in a portion of the first region. A second conductive layer is formed on the second insulating layer and the first conductive layer. The second conductive layer is etched to expose a partial surface of the first conductive layer in the first region. The second conductive layer and the first conductive layer are etched to form a reservoir capacitor in the first region and form a gate in the second region.