SiC Device Gate Built-in Resistor for High dV/dt Reliability
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Solution Overview
Problem
Silicon carbide semiconductor devices face challenges in suppressing potential differences under gate pads due to displacement currents, leading to gate oxide film deterioration and potential short-circuits between the gate and source, especially at high dV/dt conditions.
Innovation Solution
The silicon carbide semiconductor device incorporates a polysilicon gate built-in resistor with an insulating film, an interlayer insulating film, and strategically positioned gate and source contacts to divert displacement currents, preventing potential buildup and ensuring reliable operation under high dV/dt conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick field insulating film is formed under the gate built-in resistor to prevent pinholes, then manufacturing reliability is improved, but device complexity increases due to additional process steps
Solution Approach 1:
The insulating film structure is segmented into multiple layers: a first insulating film (thick field insulating film) formed before the gate built-in resistor to prevent pinholes, and a second insulating film (thin gate oxide film) formed after to provide electrical isolation. This segmentation allows each layer to serve its specific function optimally without requiring the entire structure to be overly complex.
Solution Approach 2:
The first insulating film is formed in advance (preliminarily) before forming the gate built-in resistor. This preliminary action ensures that pinhole prevention is established before subsequent processing, eliminating the need for complex post-processing repairs or additional protective measures.
2Device complexity
If the gate built-in resistor is placed directly on the substrate without interlayer insulating film to reduce device complexity, then device complexity is reduced, but reliability deteriorates due to gate-source short-circuit risk under high dV/dt conditions
Solution Approach 1:
The electrical isolation structure is segmented into two functional parts: the first insulating film that prevents pinholes and the second insulating film that provides electrical isolation between gate and source. This segmentation achieves both reliability requirements without excessive complexity.
Solution Approach 2:
The second insulating film acts as a protective cushion formed beforehand to prevent gate-source short-circuiting under high dV/dt conditions. This preliminary protective measure ensures reliability without requiring complex active protection circuits.
3Reliability
If Al or B ion implantation is applied to reduce wafer surface resistance to suppress potential difference, then electrical conductivity is improved, but manufacturing precision deteriorates due to potential damage to the gate oxide film
Solution Approach 1:
The ion implantation process is segmented into two stages: first implantation to reduce wafer surface resistance for potential difference suppression, and second implantation to repair and protect the gate oxide film. This segmentation allows both electrical performance and film integrity to be optimized.
Solution Approach 2:
The potential harm of ion implantation damaging the gate oxide film is converted into a benefit by using the implantation process to intentionally create controlled modifications that, when followed by repair implantation, result in enhanced film properties and reduced potential difference.
4Reliability
If a source wire is routed around the gate pad to suppress potential difference, then electrical conductivity is improved, but device complexity increases due to additional wiring
Solution Approach 1:
The potential difference suppression function is segmented from the wiring structure and assigned to the insulating film configuration and ion implantation regions. This allows the source wire to follow a simpler, more direct routing without compromising electrical performance.
Solution Approach 2:
The potential difference suppression function is extracted from the wiring structure and implemented through the insulating film and ion implantation. This extraction simplifies the wiring design by removing the need for complex routing arrangements.
Data Source
AI summary
A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate having an n-type drift layer, and a p-type well region formed in a surface portion of a part of the drift layer, an insulating film provided on the well region, a gate built-in resistor formed of polysilicon in contact with a surface of the insulating film, an interlayer insulating film formed on the gate built-in resistor, a gate contact wire that is connected to a gate pad and formed on the interlayer insulating film, a gate wire provided on the interlayer insulating layer so as to be apart from the gate contact wire, a first gate contact for electrically connecting the gate contact wire and the gate built-in resistor, and a second gate contact for electrically connecting the gate wire and the gate built-in resistor.