Planarized Power MOSFET Metalization via CMP
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Solution Overview
Problem
Prior art power MOSFET devices face issues with thick metalization layers that fail to effectively fill high aspect ratio gaps, leading to voids and increased fabrication costs due to the complexity of the topography and the need for extensive metalization deposition processes.
Innovation Solution
Implementing a chemical mechanical polishing (CMP) process to produce a substantially planar surface, allowing for a thin metalization layer deposition of less than 4 microns, which eliminates voids and reduces fabrication expenses by simplifying the metalization process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a thick metalization layer is used to cover the topography of prior art power MOSFET devices, then the valleys are filled to enable component interconnects, but voids still form in narrow valleys and fabrication costs increase
Solution Approach 1:
The patent applies preliminary action by performing CMP planarization before metalization deposition. This pre-flattening of the surface eliminates high aspect ratio valleys before the metalization process, ensuring complete filling without voids and reducing the required metalization thickness while maintaining reliable interconnects
2Manufacturing precision
If a thick metalization layer is deposited to cover high aspect ratio surfaces, then complete filling is attempted, but the deposition cost increases significantly
Solution Approach 1:
The patent performs CMP planarization as a preliminary step before metalization deposition. This pre-flattening reduces the surface topology variations, allowing complete filling with a much thinner metalization layer (less than 4 microns versus several microns in prior art), significantly reducing deposition costs while maintaining complete coverage
3Adaptability or versatility
If photolithography is used to define component regions with multiple layered components, then complex devices can be built, but the resulting topography resembles mountain ranges with many hills and valleys
Solution Approach 1:
The patent applies CMP planarization as a preliminary step after building the complex multi-layered device structure through photolithography. This process flattens the mountain-range-like topography created by multiple layers of components and interconnects, creating a planar surface that simplifies subsequent metalization deposition while preserving the complex device functionality
Solution Approach 2:
The patent extracts the topography problem from the device structure by applying CMP planarization. This separates the complex multi-layered device fabrication (which requires vertical structure for high voltage and current) from the surface topology issue, allowing the device to maintain its functional complexity while the surface is flattened for simplified interconnect formation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The CMP process ensures efficient filling of active areas, reduces defects, and decreases the overall cost of producing high-density power MOSFETs by eliminating the need for thick metalization layers, thereby enhancing the reliability and cost-effectiveness of the fabrication process.
Implementation Method 1
performing a CMP (chemical mechanical polishing) process on the active area to produce a substantially planar surface
Implementation Method 2
A metalization deposition process is then performed on the substantially planar surface
Data Source
AI summary
A method for producing a power MOSFET. The method includes fabricating a plurality of layers of a power MOSFET to produce an upper surface active area and performing a chemical mechanical polishing process on the active area to produce a substantially planar surface. A metalization deposition process is then performed on the substantially planar surface and the fabrication of the power MOSFET is subsequently completed.