All Bit Line Memory Array Segmentation for Program Disturb Control
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Solution Overview
Problem
All bit line memory devices face challenges in maintaining data reliability due to program disturb effects, especially as they transition from Single Level Memory Cells (SLC) to Multilevel Memory Cells (MLC), which increases with higher MLC levels, compromising the trade-off between data storage capacity and reliability.
Innovation Solution
The method involves programming and sensing memory cells in an All Bit Line (ABL) architecture, where alternating rows or tiers of memory cells are programmed as SLC or MLC concurrently, allowing for flexible programming densities across the memory array, mitigating program disturb effects and optimizing the trade-off between capacity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are programmed as MLC to increase storage capacity, then data storage density is improved, but program disturb effects increase and reliability deteriorates
Solution Approach 1:
The patent divides the memory array into multiple independent bit line groups (BL0-BL7), where each group can be independently controlled and programmed. This segmentation allows different regions to operate at different MLC levels simultaneously, enabling high-density storage in some regions while maintaining reliability in others by using lower MLC levels or SLC modes.
Solution Approach 2:
Different regions of the memory array are programmed with different MLC levels based on local requirements. For example, certain bit line groups may be programmed as MLC(2-bit) while others are programmed as MLC(3-bit) or SLC, allowing each local region to optimize for either capacity or reliability as needed.
2Productivity
If all bit lines are used for concurrent programming, then programming speed is improved, but program disturb effects worsen
Solution Approach 1:
The bit lines are divided into multiple independent groups that can be activated separately. During programming operations, only the necessary bit line groups are activated based on the access pattern, reducing the number of simultaneously active bit lines and thereby reducing program disturb effects while still maintaining high programming throughput through parallel operations on multiple groups.
Solution Approach 2:
The system dynamically selects which bit line groups to activate based on the specific programming operation being performed. This dynamic activation allows the system to optimize between speed and reliability by activating more groups for speed-critical operations and fewer groups for reliability-critical operations.
3Quantity of substance
If higher MLC levels are used, then storage capacity is improved, but program disturb effects increase
Solution Approach 1:
Different regions of the memory array are programmed with different MLC levels based on local requirements. For example, certain bit line groups may be programmed as MLC(2-bit) while others are programmed as MLC(3-bit) or SLC, allowing each local region to optimize for either capacity or reliability as needed.
Solution Approach 2:
The system changes the MLC programming level parameter dynamically based on operational requirements. By adjusting the MLC level (number of threshold voltage ranges) used in different regions or at different times, the system can optimize the balance between storage capacity and program disturb effects.
Data Source
AI summary
Devices and methods facilitate memory device operation in all bit line architecture memory devices. In at least one embodiment, memory cells comprising alternating rows are concurrently programmed by row and concurrently sensed by row at a first density whereas memory cells comprising different alternating rows are concurrently programmed by row and concurrently sensed by row at a second density. In at least one additional embodiment, memory cells comprising alternating tiers of memory cells are programmed and sensed by tier at a first density and memory cells comprising different alternating tiers of memory cells are programmed and sensed by tier at a second density.