Alternating Cell Rows With Buried Interconnects for M0 Routing

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

The increasing transistor density in semiconductor integrated circuits due to reduced component sizes and tightened spacing leads to issues of M0 routability congestion and reduced cell region density, particularly when attempting to mitigate congestion by widening cell regions.

Innovation Solution

The implementation of alternating row-architectures with buried local interconnect (BLI) structures in even rows, which reduces M0 routability congestion without increasing cell pitch, thereby maintaining cell region density.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If transistor density is increased through reduced component sizes and tightened spacing, then device integration is improved, but M0 routability congestion increases

Engineering Contradiction:

Improvetransistor densityVSAvoidM0 routability

Core Design Contradiction:

Quantity of substanceVSEase of operation

Solution Approach 1:

The device is divided into alternating first rows and second rows with different architectures. First rows contain first power grid segments and routing segments, while second rows contain second power grid segments and buried local interconnect structures. This segmentation allows routing functions to be distributed across different row types, reducing congestion in the M0 layer by providing alternative interconnect paths in buried layers for specific row types.

Inventive Principle:

Principle #1Segmentation

2Ease of operation

If cell region width is increased to mitigate M0 routability congestion, then routing efficiency is improved, but cell region density decreases

Engineering Contradiction:

Improverouting efficiencyVSAvoidcell region density

Core Design Contradiction:

Ease of operationVSQuantity of substance

Solution Approach 1:

The invention moves interconnect functionality from the planar M0 layer to buried interconnect layers beneath certain cell regions. By implementing buried local interconnect structures in second rows, the patent utilizes the vertical dimension (buried layers) to provide additional routing capacity without increasing the horizontal cell pitch, thus maintaining cell density while improving routing efficiency.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Different row types are assigned different interconnect architectures tailored to their specific routing needs. Second rows with complex routing requirements incorporate buried local interconnect structures, while first rows use standard power grid and routing segment configurations. This localized differentiation optimizes routing efficiency in specific areas without uniformly increasing cell pitch across the entire device.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS20250225304A1Device having alternating rows of corresponding first and second row-architectures and method of manufacturing same

Publication Date: 2025.07.10 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A device includes: alternating first rows and second rows correspondingly including first cell regions and second cell regions, each of the first cell regions and second cell regions correspondingly including active regions; in a first metallization layer over the active regions, each of the first cell regions and the second cell regions include first and second power grid (PG) segments, and one or more routing (RTE) segments; and in a first buried metallization layer under the active regions, each of the first cell regions includes first and second buried PG (BPG) segments, and each of the second cell regions includes one or more buried local interconnect (BLI) structures; and each of the first cell regions is free from including a BLI structure.