Computer Aided Design TRIZ Cases
- Semiconductor Pattern Layout With Mandrel Bars for Lithography Accuracy
Dummy patterns and mandrel bars improve density and uniformity in mixed-rule IC layouts while reducing lithography defects such as pinching and bridging.
- Semiconductor Layout Pattern Arrangement with Dynamic Metallization
Dynamic metallization generation lets gate and conductive patterns serve as selectable pins, expanding layout flexibility while meeting fabrication rules.
- Non-Rectangular Semiconductor Cell Layout for Denser Routing
Non-rectangular cell boundaries fit more conductive lines into the same area, expanding routing capacity and reducing design-rule violations.
- Asynchronous IC Optimization for Clock Power and Variation Robustness
Simulation-guided DTCO uses asynchronous IC domains to cut unnecessary clock transitions and improve robustness to process variation.
- Hybrid Semiconductor Verification With Power-Gating Netlists
Power-gating netlists model target blocks while RTL covers the rest, accelerating checks of wiring and power-switch operation.
- Process-Aware IC Cell Layout Generation for Yield Optimization
Manual cell libraries make yield changes unpredictable; process-aware layout generation automates high-yield cell construction.
- Short-Net Pin Alignment to Reduce IC Routing Congestion
Align adjacent-row short-net pins with heuristic and ILP stages to reduce routing congestion and limit layout disturbance in integrated circuits.
- Integrated Circuit Layout With Mixed-Height Cells And Continuous Rails
Mixed-height standard cells use aligned well boundaries and extended power and ground rails to support flexible, efficient integrated-circuit layouts.
- Integrated Circuit TAP Cell Layout for Latch-Up Immunity
Elongated TAP cells span multiple columns to improve latch-up immunity while reducing layout area at advanced process nodes.
- 3DIC Routing Graphs for Manufacturable Netlist Generation
Graph-based routing validates 3DIC configuration constraints before producing a logically equivalent, manufacturable netlist from the initial design.
- Processor Chip Timing Adjustment Using Circuit-Path Metadata
Collected path metadata and delta values identify broken circuit paths, allowing target times to change without rerunning the full design flow.