Hybrid Semiconductor Verification With Power-Gating Netlists
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Solution Overview
Problem
The increasing integration and shortened life cycles of semiconductor devices necessitate accurate, efficient, and fast verification of power-related functions and characteristics, particularly in the connection of power wiring and operation of power switches, which existing methods struggle to address effectively.
Innovation Solution
A hybrid simulation environment is created by combining a power-gating netlist (PGNET) simulation environment for target blocks with a register transfer level (RTL) simulation environment for non-target blocks, allowing for detailed power-related verification and efficient verification of power-related functions and characteristics in semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a full power-gating netlist simulation environment is used for all blocks, then power-related verification accuracy is improved, but verification time and computational resources increase significantly
Solution Approach 1:
The semiconductor device is divided into target blocks and non-target blocks. Only target blocks require detailed power-gating netlist simulation environments, while non-target blocks use simplified RTL simulation environments. This segmentation allows accurate power verification where needed while reducing overall verification time through selective application of detailed simulation.
2Measurement precision
If detailed power wiring information and power-related information are included for all blocks, then verification accuracy is improved, but device complexity and verification setup complexity increase
Solution Approach 1:
Different simulation environment qualities are applied to different blocks based on their power-related characteristics. Target blocks with power-gating functionality receive detailed power-gating netlist simulation environments with complete power wiring information, while non-target blocks use simpler RTL simulation environments. This local quality approach ensures verification accuracy is concentrated where it is most needed.
3Reliability
If verification is performed on the entire semiconductor device at once, then comprehensive coverage is achieved, but verification efficiency decreases due to the large scale
Solution Approach 1:
The verification process is segmented into two parallel tracks: detailed power-gating netlist simulation for target blocks and RTL simulation for non-target blocks. This allows comprehensive verification coverage across all blocks while improving efficiency by processing different blocks with appropriately scaled simulation methods simultaneously, rather than treating the entire device uniformly.
Data Source
AI summary
In a method of verifying a semiconductor device, input data defining the semiconductor device including a plurality of blocks is received. A first simulation environment is generated for a top module and at least one target block of the plurality of blocks in the top module. The first simulation environment includes power wiring information and additional power-related information. The top module represents an entire structure of the semiconductor device. A second simulation environment is generated for non-target blocks of the plurality of blocks other than the at least one target block. The second simulation environment is different from the first simulation environment. A verification operation is performed on the semiconductor device based on a hybrid simulation environment in which the first simulation environment and the second simulation environment are combined.