Asynchronous IC Optimization for Clock Power and Variation Robustness
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Solution Overview
Problem
Existing semiconductor design methods face challenges in optimizing performance, power consumption, and area due to process variations and limitations of synchronous designs, which lead to increased power consumption, vulnerability to process variations, and timing issues.
Innovation Solution
An integrated circuit optimization design device and method that employs an asynchronous design approach, using a design technology co-optimization (DTCO) technique to generate optimal integrated circuit structures by exploring target areas vulnerable to process variations and applying asynchronous design methods, including a simulator and optimization engine to derive optimal design parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If synchronous design method is used, then design automation is easier and timing control is simpler, but power consumption increases due to continuous clock transitions
Solution Approach 1:
The patent divides the circuit into multiple asynchronous domains that can operate independently without a global clock signal. Each domain manages its own timing, eliminating the need for continuous clock transitions across the entire circuit, thereby reducing power consumption while maintaining design automation through domain-level control.
Solution Approach 2:
The patent inverts the traditional synchronous approach by using asynchronous design methods where data flows are triggered by data availability rather than a global clock. This inversion eliminates unnecessary clock transitions and reduces power consumption while still enabling automated design through formal verification and static timing analysis tools.
2Device complexity
If synchronous design method is used, then clock signal distribution is simpler, but vulnerability to process variations increases
Solution Approach 1:
The patent segments the circuit into multiple asynchronous domains, each operating independently without relying on a global clock signal. This segmentation eliminates the distribution network for clock signals and reduces sensitivity to process variations, as each domain can tolerate larger timing variations without affecting overall system reliability.
Solution Approach 2:
The patent changes the fundamental timing parameter from a fixed global clock period to variable local timing based on data availability. This parameter change makes the design more robust to process variations, as each asynchronous domain can adapt its timing to actual signal propagation delays rather than being constrained by a fixed clock period.
3Use of energy by moving object
If asynchronous design is used, then power consumption is reduced and performance is optimized, but design automation becomes more difficult
Solution Approach 1:
The patent introduces dynamic timing control within each asynchronous domain, where timing is determined by data availability rather than a fixed clock. This dynamic approach reduces power consumption by eliminating unnecessary clock transitions while maintaining design automation through formal verification methods that can handle dynamic timing behavior.
Solution Approach 2:
The patent implements feedback mechanisms within asynchronous domains using handshake protocols and ready/valid signals. This feedback enables automated verification of data flow correctness and timing constraints, making asynchronous design more automatable while maintaining the power consumption benefits of eliminating global clock distribution.
4Ease of operation
If synchronous design is used, then timing closure is easier to achieve, but clock jitter and timing lockout problems occur
Solution Approach 1:
The patent inverts the timing closure approach by eliminating the global clock signal and using asynchronous data flow with local timing control. This inversion eliminates clock jitter and timing lockout problems inherent in synchronous designs, while timing closure is achieved through formal verification and static timing analysis at the domain level rather than global clock synchronization.
Data Source
AI summary
The present disclosure relates to an integrated circuit optimization design device including an integrated circuit design generator configured to generate an integrated circuit design, a simulator configured to simulate the integrated circuit design, and an optimization engine configured to derive an optimal design parameter for the integrated circuit design by inputting a simulation result obtained from the simulator into an optimization model provided in advance, wherein the optimal design parameter includes asynchronous design information regarding the integrated circuit design generator, and the integrated circuit design generator asynchronously generates at least a part of the integrated circuit design according to the optimal design parameter to change the integrated circuit design. Thus, an optimal integrated circuit structure robust to process variations and capable of maximizing performance may be automatically generated by applying a design technology co-optimization (DTCO)-based design optimization technique that simultaneously takes into account a semiconductor manufacturing process and design optimization.