Non-Rectangular Semiconductor Cell Layout for Denser Routing
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Solution Overview
Problem
The manufacturing of semiconductor devices becomes increasingly complex as they are miniaturized, leading to high yield loss, reduced reliability of electrical interconnection, and low testing coverage, necessitating improvements in device robustness and manufacturing efficiency.
Innovation Solution
The introduction of non-orthogonal, parallelogram-shaped semiconductor cells with non-rectangular boundaries allows for increased conductive line placement within the cell area without increasing the effective cell size, enhancing routing resources and compliance with design rules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If rectangular cells are used in semiconductor device manufacturing, then the manufacturing process is simple and standardized, but the routing resources are limited and design rule compliance is more difficult to achieve
Solution Approach 1:
The patent applies asymmetry by transitioning from conventional rectangular cells to non-rectangular parallelogram-shaped cells. This geometric transformation allows conductive lines to be positioned at angles that do not require additional routing resources, thereby improving routing flexibility while maintaining manufacturing feasibility through systematic design rule modifications
2Adaptability or versatility
If the effective cell size is increased to accommodate more conductive lines, then routing resources are improved, but the device density decreases and manufacturing complexity increases
Solution Approach 1:
The patent changes the geometric parameters of the cell shape from rectangular to parallelogrammatic, altering the internal angle measurements and side orientations. This parameter transformation enables more efficient packing of conductive lines within the same cell area, increasing routing capacity without sacrificing device density or requiring larger cell dimensions
3Productivity
If miniaturization is pursued to increase functional density, then more devices can be integrated per chip area, but manufacturing complexity increases and yield loss increases
Solution Approach 1:
The patent segments the cell design into distinct functional regions with clearly defined boundaries and internal structures. By dividing the cell into manageable segments with specific geometric characteristics, the design simplifies the manufacturing process while maintaining high functional density, making it easier to control at miniaturized scales
Data Source
AI summary
A layout method includes: generating a design data; and generating a design layout by placing a first cell. The first cell includes: a first source/drain region and a second source/drain region extending in a first direction; a first gate electrode extending in a second direction perpendicular to the first direction; and a first conductive line electrically connected to one of the first source/drain region, the second source/drain region and the first gate electrode. The first cell is defined by a left cell side and a right cell side, wherein at least one of the left cell side and the right cell side comprises a first segment extending in a third direction not parallel to the first direction and the second direction.