Processor Chip Timing Adjustment Using Circuit-Path Metadata
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Solution Overview
Problem
Existing processor chip design models face challenges in efficiently adjusting timing without redoing the entire design flow, particularly when new models are delivered with little reaction time, leading to inefficiencies and resource congestion.
Innovation Solution
Collecting metadata during the design stage, identifying broken circuit paths, and adjusting target times using delta values, with machine learning to enhance timing adjustments without full redesign.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the entire design flow is redone to adjust timing, then timing accuracy is improved, but productivity deteriorates due to time-consuming rework
Solution Approach 1:
The patent segments the design flow into distinct phases: initial timing analysis during design stage, identification of broken circuit paths, and separate timing adjustment phase. This allows timing adjustments to be made without redoing the entire design flow, improving productivity while maintaining timing accuracy through targeted adjustments of specific circuit paths.
Solution Approach 2:
The patent performs preliminary timing analysis and collects metadata during the initial design stage, identifying potential timing issues before finalization. This preliminary action enables faster subsequent adjustments by having advance knowledge of critical paths and timing parameters, avoiding the need for complete redesign.
2Adaptability or versatility
If new design models are delivered with little reaction time, then adaptability is improved, but manufacturing precision deteriorates due to insufficient timing adjustment time
Solution Approach 1:
The patent performs preliminary timing analysis and collects metadata during the initial design stage, identifying potential timing issues before finalization. This preliminary action enables faster subsequent adjustments by having advance knowledge of critical paths and timing parameters, avoiding the need for complete redesign.
Solution Approach 2:
The patent applies local quality by focusing timing adjustments on specific broken circuit paths rather than uniformly adjusting the entire design. This targeted approach allows rapid adaptation to new models while maintaining high timing precision in critical areas through focused optimization.
3Reliability
If comprehensive timing analysis is performed on all circuit paths, then reliability is improved, but device complexity increases due to processing overhead
Solution Approach 1:
The patent extracts and stores timing metadata and circuit path information during the initial design stage. This extraction allows subsequent timing analyses to use pre-collected data without reprocessing the entire design, reducing computational complexity while maintaining comprehensive verification of all circuit paths.
Solution Approach 2:
The patent performs preliminary timing analysis and collects metadata during the initial design stage, identifying potential timing issues before finalization. This preliminary action enables faster subsequent adjustments by having advance knowledge of critical paths and timing parameters, avoiding the need for complete redesign.
Data Source
AI summary
Data relating to one or more circuit paths may be collected during a design stage of a processor chip based on a design model. One or more delta values may be added to the one or more circuit paths of the design model. One or more broken circuit paths may be identified based on the one or more delta values. A target time for each of the one or more broken circuit paths may be adjusted.