Short-Net Pin Alignment to Reduce IC Routing Congestion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing routing technologies face challenges in aligning short net pins efficiently, particularly for integrated circuits, leading to suboptimal routing and increased congestion.
Innovation Solution
A method involving heuristic and Integer Linear Programming (ILP) operations is employed to align short nets by shifting gates within a threshold, minimizing disturbance and optimizing routing, using a two-stage flow to handle large problem sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing routing technologies are used for aligning short net pins, then routing operations can be executed, but alignment efficiency is poor and congestion increases
Solution Approach 1:
The patent segments the routing problem into two distinct stages: a heuristic operation stage for initial alignment and an Integer Linear Programming (ILP) operation stage for optimization. This segmentation allows each stage to focus on specific aspects of the alignment problem, improving overall routing efficiency while managing complexity through divided computational tasks.
Solution Approach 2:
The patent performs preliminary alignment actions by identifying and aligning short net pins before executing the main routing operation. The heuristic operation conducts preliminary adjustments to gate positions, preparing the layout for subsequent ILP optimization and reducing congestion before the final routing phase.
2Manufacturing precision
If gate positions are shifted to align short nets, then routing improvement is achieved, but disturbance to the design increases
Solution Approach 1:
The patent applies local quality by focusing alignment operations specifically on short net pins rather than uniformly adjusting all gate positions. The heuristic and ILP operations identify and selectively adjust only those gates involved in short nets, achieving precise pin alignment while minimizing disturbance to the overall design layout.
Solution Approach 2:
The patent changes positional parameters of gates selectively to achieve pin alignment. The ILP operation optimizes the displacement parameters of gates involved in short nets, making precise parameter adjustments that improve alignment while controlling the extent of design changes through mathematical optimization constraints.
Data Source
AI summary
Embodiments are provided for providing enhanced routing in a computing system by a processor. One or more of a plurality of short nets in a cell of an integrated circuit may be aligned for executing a routing operation, wherein a short net is a two-pin net having two gates on adjacent rows having a horizontal distance less than a selected threshold.