Alternating Chip-Stack Layout for Thermal-Warpage Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
There is a limit to the high integration of semiconductor devices, and stacked semiconductor packages face challenges in maintaining structural reliability due to thermal expansion differences and warpage.
Innovation Solution
A stacked semiconductor package design with alternating horizontal shifts in chip stacks and a controller chip configuration that reduces thermal expansion coefficient differences, using bonding wires and connection structures to secure electrical connections and structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are stacked to achieve high integration and large capacity, then the storage capacity and integration density are improved, but thermal expansion differences and structural reliability issues worsen
Solution Approach 1:
The chip stack is divided into multiple sub-stacks with alternating shift directions, where each sub-stack contains chips shifted in a specific horizontal direction. This segmentation allows differential thermal expansion to be managed locally within each sub-stack while maintaining overall structural integrity across the entire package.
Solution Approach 2:
Adjacent chip stacks are intentionally shifted in opposite horizontal directions to create an asymmetric configuration. This asymmetric arrangement compensates for thermal expansion differences between adjacent stacks, as the opposing shift directions create balanced stress distribution that prevents warpage and maintains structural reliability during thermal cycling.
2Reliability
If chip stacks are shifted in opposite directions to reduce thermal warpage, then structural reliability is improved, but manufacturing precision requirements worsen
Solution Approach 1:
The shift interval between adjacent chips is optimized locally within each sub-stack to be smaller than the chip length, ensuring proper electrical connection while managing thermal expansion. This local optimization allows the alternating shift pattern to be implemented without requiring extreme precision across the entire package, as each local connection point can be independently controlled.
Solution Approach 2:
The shift interval parameter is varied between sub-stacks to create the alternating shift pattern. By controlling this parameter to be less than the chip length but allowing different values in adjacent sub-stacks, the design achieves thermal warpage reduction while maintaining manufacturability through standard alignment tolerances.
3Reliability
If bonding wires are used to electrically connect stacked chips, then electrical connectivity is achieved, but the complexity of maintaining reliable connections across multiple stacked chips increases
Solution Approach 1:
Multiple chip stacks are vertically nested on the package base substrate, with each sub-stack containing sequentially arranged chips. The bonding wires connect chips within each sub-stack and between sub-stacks in a nested configuration, where connection paths are organized hierarchically from individual chips to sub-stacks to the complete package, simplifying the overall connection architecture.
Solution Approach 2:
The chip stacks are arranged in the vertical dimension with horizontal shifts, creating a three-dimensional connection architecture. This vertical stacking with horizontal offset allows bonding wires to connect chips at different levels and positions, reducing the complexity of planar routing while maintaining reliable electrical connectivity through spatial optimization.
Data Source
AI summary
A stacked semiconductor package may include a package base substrate, a first chip stack including a first semiconductor chips stacked sequentially on the package base substrate, a second chip stack including second semiconductor chips stacked sequentially on the first chip stack, and bonding wires electrically connecting the first semiconductor chips and the second semiconductor chips to the package base substrate. Each of the first semiconductor chips may be shifted by a first interval in a first horizontal direction to have a step shape. Each of the second semiconductor chips may be shifted by the first interval in a second horizontal direction, opposite to the first horizontal direction, to have a step shape. A lowermost second semiconductor chip may be shifted from an uppermost first semiconductor chip by a second interval in the second direction. The second interval may be greater than the first interval.