Alternating Conductive Bumps for Semiconductor Package Stacking
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving miniaturization, high performance, and high capacity while maintaining reliability, particularly in the efficient connection and stacking of semiconductor chips, which can lead to short-circuits during reflow or thermal compression bonding processes.
Innovation Solution
The semiconductor package design includes a configuration of conductive bumps and pillars at different levels, alternately disposed to prevent short-circuits, with insulating layers and specific materials like nickel, copper, and gold used to enhance connectivity and reliability, allowing for the efficient stacking and connection of multiple semiconductor chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor packages use standard connection methods, then manufacturing is simpler, but reliability deteriorates due to short-circuits during reflow or thermal compression bonding processes
Solution Approach 1:
The patent introduces alternating levels (different vertical positions) for conductive bumps in adjacent connection members. This dimensional variation in the vertical direction prevents short-circuits during reflow or thermal compression bonding while maintaining electrical connectivity, thus improving reliability without excessive complexity
Solution Approach 2:
The connection structure is divided into multiple connection members, each with conductive bumps at different alternating levels. This segmentation allows each connection member to be independently designed and positioned, preventing short-circuits between adjacent connections while maintaining overall structural organization
2Volume of moving object
If semiconductor chips are miniaturized and stacked to achieve high capacity, then device size is reduced, but manufacturing precision requirements increase to prevent short-circuits
Solution Approach 1:
By utilizing the vertical dimension with alternating bump levels, the patent enables miniaturized stacked packages while maintaining manufacturing feasibility. The alternating levels provide inherent spacing that reduces the precision required for horizontal alignment during assembly, allowing high-capacity stacking without excessive manufacturing difficulty
Solution Approach 2:
The insulating layer serves as an intermediary between conductive bumps at different levels, providing electrical isolation and mechanical support. This intermediary structure enables closer spacing of connection members while preventing short-circuits, thus allowing miniaturization without compromising manufacturing precision requirements
Data Source
AI summary
A semiconductor package includes a first semiconductor chip having a plurality of first through-electrodes and a plurality of first upper connection pads respectively connected to the plurality of first through-electrodes, where the plurality of first upper connection pads are on an upper surface of the first semiconductor chip, a second semiconductor chip on the first semiconductor chip and having a plurality of second lower connection pads on a lower surface of the second semiconductor chip, and a plurality of connection members, each including a pillar and a conductive bump, the plurality of connection members electrically connecting respective ones of the first upper connection pads and the second lower connection pads to each other. Conductive bumps of adjacent connection members, among the plurality of connection members, are alternately disposed at different levels with respect to the upper surface of the first semiconductor chip.