Alternating Pillar Semiconductor Device Edge Termination
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Solution Overview
Problem
Semiconductor devices with charge compensation structures face high switching losses due to stored output charge and output capacitance, which can lead to significant switching delays and increased costs associated with edge-termination structures that consume chip area.
Innovation Solution
The semiconductor device incorporates a field-effect semiconductor body with alternating n-type and p-type drift portions and compensation regions in the active area, and a p-type edge termination region in the peripheral area with a lower doping concentration, allowing for reduced output capacitance and improved switching efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If edge-termination structures are used to achieve high breakdown voltages, then breakdown voltage is improved, but chip area increases
Solution Approach 1:
The patent implements local quality differentiation by creating low-doped edge termination regions specifically at the periphery while maintaining high-doped compensated drift portions in the active area. This allows high breakdown voltage performance at the edges without requiring the entire chip area to be dedicated to termination structures.
Solution Approach 2:
The patent segments the semiconductor device into distinct functional regions: active area with compensated drift portions for current conduction, and peripheral area with low-doped edge termination regions for voltage blocking. This segmentation allows each region to be optimized independently, reducing the area required for edge termination while maintaining breakdown voltage performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces switching losses and delays while minimizing chip area usage, enhancing the semiconductor device's performance and cost-effectiveness by optimizing the edge termination structure.
Implementation Method 1
The compensation principle is based on a mutual compensation of charges in n- and p-doped regions, which are often also referred to as n- and p-doped pillar regions, in the drift zone of a vertical MOSFET.
Implementation Method 2
arranged next to one another in the semiconductor volume of the semiconductor device or interleaved with one another in such a way that, in the off-state, their charges can be mutually depleted
Implementation Method 3
The drift portions have a first maximum doping concentration and are in Ohmic contact with the drain metallization
Data Source
AI summary
In a field-effect semiconductor device, alternating first n-type and p-type pillar regions are arranged in the active area. The first n-type pillar regions are in Ohmic contact with the drain metallization. The first p-type pillar regions are in Ohmic contact with the source metallization. An integrated dopant concentration of the first n-type pillar regions substantially matches that of the first p-type pillar regions. A second p-type pillar region is in Ohmic contact with the source metallization, arranged in the peripheral area and has an integrated dopant concentration smaller than that of the first p-type pillar regions divided by a number of the first p-type pillar regions. A second n-type pillar region is arranged between the second p-type pillar region and the first p-type pillar regions, and has an integrated dopant concentration smaller than that of the first n-type pillar regions divided by a number of the first n-type pillar regions.