ALU Fault Tolerance via SIMD Input Replication
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Solution Overview
Problem
Fault tolerance and detection features are not typically implemented in data-transformation units like arithmetic-logic units (ALUs) in high-production processors due to high implementation costs, despite increased transistor density and fault probabilities from alpha particles and other factors.
Innovation Solution
The implementation of SIMD hardware for redundant ALU operations, where inputs are replicated and processed in parallel across multiple execution units, with results compared for fault detection and majority voting for fault tolerance, ensuring negligible hardware and software performance impact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fault tolerance and detection features are implemented in ALUs, then reliability is improved, but device complexity and implementation cost increase
Solution Approach 1:
The patent merges fault detection and tolerance functionality with existing SIMD execution units by replicating input operands across multiple execution units and comparing their outputs. This integration allows fault detection without requiring separate dedicated fault detection hardware, thereby improving reliability while minimizing additional device complexity.
Solution Approach 2:
The patent creates copies of input operands and routes them to multiple execution units performing the same operation. By comparing the outputs of these replicated operations, the system can detect faults. This copying approach enables fault detection using existing hardware resources rather than adding complex new detection circuits.
2Reliability
If redundant ALU operations are performed in parallel, then fault detection capability is improved, but hardware overhead increases
Solution Approach 1:
The patent makes existing SIMD execution units perform dual functions: normal computation and fault detection through replicated operations. The same execution units that perform standard arithmetic and logic operations are also used to execute replicated operations for fault detection, eliminating the need for dedicated fault detection hardware and reducing overall hardware overhead.
Solution Approach 2:
The system uses its own existing execution units to perform fault detection rather than requiring external or separate detection hardware. The execution units serve themselves by executing replicated operations and providing their outputs for comparison, thereby enabling fault detection capability without increasing hardware overhead.
3Reliability
If input operands are replicated and processed in parallel, then fault tolerance is improved, but processing time may increase
Solution Approach 1:
The patent maintains continuous useful action by performing replicated operations in parallel within the same clock cycle as normal operations. The SIMD execution units process replicated operands simultaneously with regular operands, and the comparison of results occurs without interrupting the normal processing flow, thereby achieving fault tolerance without increasing processing time.
Solution Approach 2:
The patent applies partial replication where only necessary portions of operations are duplicated for fault detection. By selectively replicating operations based on their fault-criticality and using the existing parallel processing capability of SIMD units, the system achieves adequate fault tolerance while minimizing the time overhead associated with additional processing.
Data Source
AI summary
Systems, methods, and apparatuses for fault tolerance and detection are described. For example, an apparatus including circuitry to replicate input sources of an instruction; arithmetic logic unit (ALU) circuitry to execute the instruction with replicated input sources using single instruction, multiple data (SIMD) hardware to produce a packed data result; and comparison circuitry coupled to the ALU circuitry to evaluate the packed data result and output a singular data result into a destination of the instruction is described.