Single Instruction Multiple Data Multiprocessors TRIZ Cases
- Indirect Branch Instruction for SIMT Function Calls
An indirect branch instruction enables function calls in single-instruction multiple-thread processors by accepting address registers as arguments.
- Unified Shader Core for Graphics Processor Load Balancing
A unified shader core balances vertex and pixel loads by executing diverse programs on shared clusters, reducing idle cycles in graphics processors.
- Super-Descriptor Engine Chaining in SoC Storage Controllers
Chaining engines via a super-descriptor reduces firmware overhead and enhances throughput by enabling autonomous data flow processing.
- Parallel Memory Banks with Shifted Storage Scheme
Parallel memory banks with a shifted storage scheme resolve silicon area and power bottlenecks while boosting processing throughput for SIMD processors.
- Vectorized Heapsort Using Horizontal Aggregation SIMD
Horizontal aggregation SIMD instructions accelerate sorting speed by reducing comparisons in K-heaps, resolving sequential processing bottlenecks.
- Contention-Free Routing for NTT/iNTT Tile Arrays
A parallel processing device implements contention-free routing schedules to optimize data movement across tile arrays.
- Configurable Multi-Core Image Processor with Dynamic Internal Network
A multi-core image processor uses a configurable internal network to dynamically couple specific cores for targeted execution.
- Random Matrix Hardware for Efficient Neural Network Training
A random matrix network simplifies backpropagation using fixed weight matrices for faster learning.