Min/Max Collector Hardware for VPU Anomaly Detection
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Solution Overview
Problem
Conventional vector processing units (VPUs) face inefficiencies in detecting minimum and maximum values, operand sharing among data lanes, memory access, data manipulation, table lookups, and fault detection, leading to increased latency and processing complexity in applications like computer vision and deep learning.
Innovation Solution
The proposed solution includes a min/max hardware collector, automatic predication, SIMD architecture with lane communication, transposed load/store operations, load with permute instructions, and a decoupled lookup table accelerator, along with a hardware sequencer for DMA systems, to optimize data movement and processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If all computed values are written to memory for min/max detection, then complete data is available for analysis, but additional processing cycles and latency are required
Solution Approach 1:
The min/max collector hardware performs preliminary min/max detection during the data writing process itself, rather than waiting until all data is written to memory. The collector continuously tracks minimum and maximum values as data flows through the memory interface, making the detection happen in parallel with the memory write operation. This eliminates the need for a separate analysis pass after memory writing completes.
Solution Approach 2:
A dedicated min/max collector hardware component is introduced as an intermediary between the memory system and the processing logic. This collector intercepts data during the memory write operation and performs min/max detection independently, then provides results to the anomaly detection logic without requiring the main processor to wait for or re-read the data from memory.
2Productivity
If SIMD units operate independently in parallel, then processing throughput is high, but operand sharing between lanes is restricted and requires copying
Solution Approach 1:
Adjacent SIMD lanes are merged into a shared data path structure that allows multiple lanes to access common operands without full replication. The patent implements a sharing network that combines inputs from multiple lanes and distributes them efficiently, reducing the total number of operand copies needed while maintaining parallel processing capability.
Solution Approach 2:
The data path is designed with universal sharing structures that can serve multiple SIMD lanes simultaneously. A single operand storage location can be accessed by multiple lanes through the sharing network, making the system multi-functional in terms of operand distribution. This universal access mechanism eliminates the need for dedicated copies of the same operand in each lane.
3Ease of operation
If memory reads use standard vector processing width, then memory access is simplified, but additional values are read unnecessarily when memory bank is wide
Solution Approach 1:
The memory access operation is segmented into multiple smaller read operations that match the actual data requirements. Instead of reading a full vector width from memory, the system divides the read into smaller chunks that correspond to the specific elements needed, reducing unnecessary data transfer from memory while maintaining simple access patterns through regular addressing.
4Adaptability or versatility
If additional data manipulation instructions are used, then data can be reorganized for operations, but additional cycles and latency are required
Solution Approach 1:
The load and permutation operations are merged into a single unified instruction that performs both data loading and reorganization in one atomic operation. The patent implements a load-permute instruction that combines the memory load function with an immediate permutation operation, eliminating the sequential execution of separate load and permute instructions and their associated latency.
5Productivity
If tables are replicated for each value or additional read ports are added, then table lookup performance improves, but additional memory and chip space are required
Solution Approach 1:
Instead of physically replicating entire lookup tables for each processing lane, the system creates virtual copies through a sharing network that allows multiple lanes to access the same physical table structure simultaneously. The patent implements a table sharing mechanism where a single table instance can serve multiple SIMD lanes through time-multiplexed or spatial-multiplexed access, eliminating the need for duplicate table storage.
Data Source
AI summary
In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.