Image Processor Architecture with Execution Lanes and 2D Shift Registers
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Solution Overview
Problem
Traditional image processors either consume high energy due to versatile software development platforms or lack versatility due to fixed-function custom circuits, with no technology providing a balance between both.
Innovation Solution
A unique image processor architecture featuring an array of execution lanes coupled with a two-dimensional shift register array, allowing simultaneous processing of overlapping image stencils and efficient data handling through a network of stencil processors and line buffer units, with credit control mechanisms to manage data flow and prevent resource overload.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If general purpose processor with vector instruction enhancements is used, then versatility of application software development platform is improved, but energy consumption per unit of data increases
Solution Approach 1:
The processor is divided into multiple execution lanes (e.g., 32 lanes) that can operate independently and simultaneously. Each lane can execute the same instruction on different data elements, enabling fine-grained parallel processing. This segmentation allows the system to maintain versatility through programmable execution lanes while reducing energy consumption by distributing work across multiple specialized units rather than over-provisioning a general-purpose core.
Solution Approach 2:
The patent introduces a two-dimensional array structure where execution lanes are arranged in a grid pattern with row and column indices. This 2D organization enables simultaneous processing of image data in both horizontal and vertical directions, adding a spatial dimension to the processing capability. The dimensional expansion allows the processor to handle complex image operations efficiently while maintaining programmability, thus achieving both versatility and energy efficiency.
2Use of energy by moving object
If fixed function hardwired circuitry is used, then power consumption per unit of data is reduced, but versatility of tasks that the processor can perform decreases
Solution Approach 1:
The execution lanes are designed as universal processing units that can be configured to perform different operations through programmable control. Each lane contains arithmetic logic units, data memory, and control logic that can be directed to execute various image processing algorithms. This universal design allows a single hardware structure to replace multiple specialized fixed-function circuits, maintaining low power consumption while achieving task versatility through software programming.
Solution Approach 2:
The processor employs dynamic configuration where execution lanes can be selectively activated or deactivated based on the specific processing task requirements. The control logic dynamically routes data and instructions to appropriate lanes, and lanes can be programmed with different operations on-the-fly. This dynamic adaptability allows the system to optimize power consumption for each task by activating only the necessary processing units while maintaining the capability to perform diverse image processing operations.
3Use of energy by moving object
If larger units of data are applied to custom designed circuits, then power consumption per unit of data is reduced, but the set of performable tasks becomes limited
Solution Approach 1:
The processor is designed to continuously process data streams through pipelined execution lanes that operate without idle cycles. Data flows continuously through the execution lanes in a pipeline manner, with each lane processing different stages of the computation. This continuous operation maximizes the utilization of processing resources, ensuring that power consumption is efficiently utilized for productive work, while the programmable nature maintains task versatility.
Data Source
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AI summary
A processor is described. The processor includes a network. A plurality of processing cores are coupled to the network. The processor includes a transmitter circuit coupled to the network. The transmitter circuit is to transmit output data generated by one of the processing cores into the network. The transmitter circuit includes control logic circuitry to cause the transmitter circuit to send a request for transmission of a second packet of output data prior to completion of the transmitter circuit's transmission of an earlier first packet of output data.