SIMD Bitonic Merge Sorting Ascending Descending Registers
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Solution Overview
Problem
Existing sorting and merging algorithms for arrays on Single Instruction Multiple Data (SIMD) processors are inefficient, particularly when dealing with large datasets, as they require additional reverse operations that increase computational complexity and execution costs.
Innovation Solution
A modified bitonic merge operation is performed on SIMD processors, where values are sorted in ascending order in one register and descending order in another, eliminating the need for reverse operations by exchanging minimum and maximum instructions in comparisons, thus generating merged output without additional execution cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional sorting and merging algorithms are used on SIMD processors, then the operations can be performed, but additional reverse operations are required which increase computational complexity and execution time
Solution Approach 1:
The patent applies inversion by generating two outputs from the bitonic merge operation: one in ascending order and another in descending order. Traditionally, only ascending order was generated requiring a reverse operation to obtain descending order. By inverting the approach to simultaneously produce both orders, the patent eliminates the need for separate reverse operations, reducing computational complexity while improving productivity
2Productivity
If traditional bitonic merge operation is used, then merging can be performed, but reverse operations are needed to generate descending order output which increases execution time
Solution Approach 1:
The patent applies preliminary action by modifying the bitonic merge operation to pre-generate both ascending and descending order outputs in a single operation. Instead of performing a reverse operation after obtaining ascending order output, the system preliminarily prepares both orderings simultaneously during the merge process itself, thereby reducing execution time and eliminating redundant operations
3Device complexity
If minimum and maximum instructions are exchanged in comparisons, then descending order output can be generated directly, but the comparator logic must be modified
Solution Approach 1:
The patent applies parameter changes by swapping the roles of minimum and maximum instructions in the comparator logic. Instead of using traditional comparison logic that extracts minimum values, the modified bitonic merge operation uses maximum extraction for certain comparisons and minimum extraction for others. This parameter swap in the instruction behavior enables direct generation of descending order output while maintaining the overall structure of the bitonic merge algorithm
Data Source
AI summary
A computer-implemented method is provided for performing bitonic merge operations. The computer-implemented includes receiving a plurality of first values in a first hardware register from a first input stream in ascending order, receiving a plurality of second values in a second hardware register from a second input stream in descending order, performing a bitonic merge operation on the first and second values in the first and second hardware registers, and reversing comparison operations performed by one or more comparators in the bitonic merge operation, outputs of the one or more comparators being loaded into the second hardware register so that output values of the second hardware register are arranged in descending order and placed into an output stream.