Digital Signal Processor Matrix Dedicated Write Resources
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Solution Overview
Problem
Integrated circuits with multiple digital signal processors face bottlenecks in data communication due to shared bus resources, leading to reduced processing speed and increased conflicts.
Innovation Solution
Implementing a local read/remote write scheme with dedicated write resources and buffer memory areas, where each digital signal processor has its own group of neighbors for writing, and using an arbiter for resource arbitration to minimize conflicts and optimize communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a common shared bus is used for data communication between all digital signal processors, then device complexity is reduced, but processing speed decreases due to bus conflicts and bottleneck effects
Solution Approach 1:
The patent divides the communication structure into dedicated write resources and shared read resources. Each digital signal processor has dedicated write connections to specific target processors, eliminating write conflicts on shared buses. Read operations continue to use shared resources, maintaining simplicity. This segmentation resolves the contradiction by isolating the conflict-prone write operations from shared resources.
Solution Approach 2:
The patent implements local quality by providing each digital signal processor with dedicated write resources tailored to its specific communication needs. Instead of a uniform shared bus for all processors, each processor has customized dedicated connections to its target processors, optimizing local communication paths while maintaining overall system simplicity through shared read resources.
2Productivity
If dedicated write resources are provided for each digital signal processor, then processing speed increases by reducing bus conflicts, but device complexity increases
Solution Approach 1:
The patent segments communication resources into dedicated write paths and shared read paths. This segmentation allows the system to gain the performance benefits of dedicated resources for write operations (which cause conflicts) while avoiding the complexity of dedicating all resources, thereby resolving the contradiction between speed and complexity.
Solution Approach 2:
The patent applies universality by using shared read resources that serve multiple digital signal processors simultaneously. This multi-functional approach reduces overall device complexity while dedicated write resources handle the conflict-prone operations, achieving a balance between performance and complexity.
3Ease of manufacture
If a shared bus is used for data communication, then ease of manufacture is improved, but reliability decreases due to bus conflicts and arbitration requirements
Solution Approach 1:
By segmenting write operations onto dedicated resources, the patent eliminates the arbitration logic and conflict handling required in shared bus systems. This segmentation improves reliability by removing the sources of communication errors while maintaining manufacturing simplicity through the use of shared read resources for the remaining operations.
4Adaptability or versatility
If the number of connections is increased to provide full connectivity between processors, then adaptability increases, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent implements local quality by providing dedicated write connections only between processors that have specific communication requirements. This customized approach maintains adaptability for data-flow applications where processors communicate in predictable patterns, while avoiding the complexity of full connectivity by making connections local and targeted rather than universal.
Data Source
AI summary
A plurality of digital signal processors (10), each contains a signal processing core (22), a memory (20) coupled to the processing core (22) and a multiplexed data input (16) coupled to the memory (20). Each digital signal processor has a plurality of outputs for outputting data from the signal processing core (22). A remote write only structure (14a-d) couples outputs of respective groups of the digital signal processors (10) each to the multiplexed data input (16) of respective particular digital signal processor (10), the respective group for the particular digital signal processor (10) not including the particular digital signal processor (10). Thus, each processor (10) writes data for other processors directly from the processor, without storing the data in memory first for handling by an I/O processor, and reads data from other processors (10) via memory, where it is received via an input that does not share resources with the output of the processor (10).