Multi-Stage Crossbar Switch for Graphics Pipeline
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Solution Overview
Problem
Current implementations of shared local memory crossbars in graphics processing pipelines require a large gate count and cause timing issues due to high fanout, especially when dealing with multiple SIMD processors and a large number of slots and banks.
Innovation Solution
Implementing a multi-stage crossbar switch array with three levels of crossbar switches, where the first level has r n×m switches, the middle level has m r×p switches, and the last level has p m×k switches, with specific connections between levels to reduce the number of multiplexer cells and simplify multiplexer selection logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a monolithic data crossbar is implemented with N:1 multiplexers for every output port, then complete routing capability is achieved, but the gate count increases significantly and timing issues occur due to large fanout
Solution Approach 1:
The crossbar is divided into multiple stages (first level with r n×m switches, middle level with m r×p switches, last level with p m×k switches) instead of using a single monolithic crossbar. This segmentation reduces the fanout requirement for individual multiplexers and decreases the overall gate count while maintaining complete routing capability between s input ports and b output ports.
Solution Approach 2:
The invention transitions from a two-dimensional N×M crossbar view to a three-dimensional multi-stage architecture by adding the middle level of crossbar switches. This dimensional expansion allows data to flow through multiple levels (first level → middle level → last level), reducing the complexity of individual switching stages while achieving the same routing functionality.
2Adaptability or versatility
If a monolithic data crossbar is implemented with N:1 multiplexers for every output port, then complete routing capability is achieved, but timing issues occur due to large fanout
Solution Approach 1:
By segmenting the crossbar into multiple stages, the fanout of individual multiplexers is reduced from N to smaller values (n, m, k). This reduction in fanout decreases the propagation delay through each multiplexer stage, improving overall timing performance while maintaining the ability to route any input to any output through the multi-stage structure.
Solution Approach 2:
The middle level of crossbar switches acts as an intermediary between the first level and the last level. Data flows through this intermediate stage, which breaks the direct N:1 multiplexer connection into smaller, more manageable routing steps. This intermediary structure reduces the timing burden on individual multiplexers while preserving complete routing capability.
3Productivity
If the number of SIMD slots and memory banks is increased to handle more data, then processing capacity is improved, but the number of multiplexer cells required increases exponentially
Solution Approach 1:
The multi-stage crossbar architecture segments the routing function across multiple levels, allowing the system to scale to more SIMD slots (s) and memory banks (b) without requiring an exponential increase in multiplexer cells. Each stage handles a portion of the routing task, distributing the complexity across r n×m switches, m r×p switches, and p m×k switches.
Solution Approach 2:
The invention changes the structural parameters of the crossbar from a single-stage N×M configuration to a multi-stage configuration characterized by parameters r, n, m, p, k where s=r×n and b=p×k. This parameter transformation allows the system to achieve higher processing capacity (more slots and banks) while controlling the multiplexer cell count through the distributed architecture.
Data Source
AI summary
A shared local memory data crossbar may be implemented in multiple stages. With this approach, the number of multiplexer cells can be reduced by fifty percent (50%) or more in some embodiments.