Digital Signal Processor Compute Array Architecture
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Solution Overview
Problem
Current digital signal processors face limitations in performance and flexibility, particularly in high-performance applications like base stations in wireless systems, where they require increased computation speed, reduced power dissipation, and optimized memory access, often necessitating the use of expensive ASICs or FPGAs, which lack flexibility and are inefficient in next-generation wireless systems.
Innovation Solution
A digital signal processor architecture featuring a control block and a compute array with multiple compute engines, where instructions flow through successive engines, enabling column-by-column, row-by-column, and row-by-row operations, with memory configurations that allow data recirculation and grouping of compute engines for enhanced performance and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If digital signal processors are used in combination with ASICs and FPGAs to meet performance requirements, then computation speed is improved, but device complexity and cost increase
Solution Approach 1:
The processor is divided into multiple compute engines (CE0-CE7) organized in a compute array, with each engine capable of independent operation. This segmentation allows parallel processing while maintaining modular complexity, resolving the contradiction by distributing computational tasks across multiple simpler units rather than requiring a single complex processor-ASIC-FPGA combination
Solution Approach 2:
Each compute engine is designed with universal functionality to handle various digital signal processing operations including FIR filters, IIR filters, FFTs, and matrix operations. The compute engines can be configured for different applications through programmable control, eliminating the need for application-specific hardware customization while maintaining high performance
2Speed
If digital signal processors are used in combination with ASICs and FPGAs to meet performance requirements, then computation speed is improved, but cost increases
Solution Approach 1:
The processor provides a universal platform that can be manufactured as a standard integrated circuit without requiring expensive ASIC or FPGA customization. The programmable architecture allows a single manufactured design to serve multiple applications, reducing development and manufacturing costs while achieving high computation speeds through parallel execute capability
Solution Approach 2:
Multiple identical compute engines are replicated within the processor array, allowing parallel execution of the same or different instructions. This copying approach enables high-performance computation through parallelism while using standardized, manufacturable components rather than expensive custom hardware
3Productivity
If high performance is achieved through increased computation speed, then productivity is improved, but power dissipation increases
Solution Approach 1:
The compute engines operate in a pipelined manner where instructions flow through successive engines at successive times, creating a periodic execution pattern. This allows the system to maintain high throughput performance while individual engines can enter low-power states between execution cycles, reducing overall power dissipation compared to continuously active high-performance processors
Solution Approach 2:
By dividing the computational workload across multiple segmented compute engines that execute instructions sequentially in a pipeline, the processor achieves high productivity through parallel throughput while each individual engine operates at lower power levels, reducing total power dissipation compared to a single high-performance engine operating continuously
4Speed
If instructions execute in successive compute engines at successive times, then processing speed is improved through parallel execution, but device complexity increases
Solution Approach 1:
Multiple compute engines share common resources including a unified control block, instruction memory, and data memory structures. This merging of resources reduces the overall architectural complexity compared to having fully independent engines, while still enabling parallel execution and high processing speed through coordinated operation of the shared resources
Data Source
AI summary
A digital signal processor includes a control block configured to issue instructions based on a stored program, and a compute array including two or more compute engines configured such that each of the issued instructions executes in successive compute engines of at least a subset of the compute engines at successive times. The digital signal processor may be utilized with a control processor or as a stand-alone processor. The compute array may be configured such that each of the issued instructions flows through successive compute engines of at least a subset of the compute engines at successive times.