Asynchronous Processor Architecture Segments Memory Addressing
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Solution Overview
Problem
Conventional computing devices face inefficiencies in processing power due to limitations in memory access operations, where a single memory location can only be accessed by a single arithmetic logic unit (ALU) in one direction during a computing cycle, and simultaneous read and write operations are not possible, leading to poor economy in computing cycles.
Innovation Solution
A data processing method that dissociates memory address updating and computing operations, allowing ALUs to perform computing operations asynchronously and self-adaptively, with memory addresses updated in local memory units separately from computing operations, enabling faster processing by relieving ALUs from addressing tasks and reducing the overall processing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory access operations are performed synchronously with computing operations, then the bus can be fully utilized for data transfer, but the ALUs must wait for memory operations to complete, reducing overall processing speed
Solution Approach 1:
The patent segments the processing functions by separating memory address updating operations from computing operations. Different ALUs are assigned to different tasks: some ALUs update memory addresses while others perform computing operations. This segmentation allows parallel execution of memory management and computing tasks, eliminating the waiting time that would occur in a synchronous system where all ALUs must wait for memory operations to complete.
Solution Approach 2:
The patent implements preliminary action by updating memory addresses in advance before computing operations are executed. The control unit updates memory addresses in local memory units prior to initiating computing operations, so that when data needs to be accessed during computing, the addresses are already prepared and available. This eliminates the need for ALUs to wait during computing operations for address updates to occur.
2Productivity
If a single memory location is accessed by a single ALU in one direction during a computing cycle, then the bus structure remains simple, but the memory access efficiency is limited and computing cycles are wasted
Solution Approach 1:
The patent segments memory access operations by separating address updating functions from data access functions. Different ALUs handle different aspects of memory operations: some ALUs are dedicated to updating addresses in local memory units while others access data using those addresses. This segmentation enables multiple memory operations to occur in parallel without requiring complex bus arbitration, maintaining relatively simple bus structures while improving access efficiency.
Solution Approach 2:
The patent introduces local memory units as intermediary structures between the bus and main memory. These local memory units store address information and allow ALUs to perform address updates and data accesses without directly competing for bus access at every operation. The local memory units act as buffers that decouple the timing and direction of different memory operations, enabling more efficient memory access patterns without proportionally increasing bus complexity.
3Productivity
If simultaneous read and write operations are not permitted on the same memory location, then data integrity is maintained, but additional computing cycles are required and processing efficiency decreases
Solution Approach 1:
The patent segments the ALU population into different functional groups: some ALUs are assigned to perform read operations while others perform write operations on the same memory locations. This segmentation allows simultaneous read and write operations to occur on the same memory location without conflict, as different ALUs handle different operation types. The control unit coordinates these segmented ALUs to ensure data integrity while maximizing parallel operation throughput.
Solution Approach 2:
The control unit implements self-service by automatically managing the coordination of simultaneous read and write operations without requiring external intervention or complex arbitration. When a memory location is designated for both reading and writing in the same computing cycle, the control unit autonomously manages the operations to ensure data integrity, allowing the system to maintain high processing efficiency without additional computing cycles being wasted on arbitration or conflict resolution.
Data Source
AI summary
A data processing method comprising: a control unit, at least one ALU, a set of registers, a memory and a memory interface. The method comprises: a) obtaining the memory addresses of the operands; b) reading the operands from memory; c) transmitting an instruction to execute computing operations to the ALU without any addressing instruction; d) executing all of the elementary operations by way of the ALU receiving, at input, each of the operands from the registers; e) storing the data forming results of the processing operation on the registers; f) obtaining a memory address for each of the data forming a result of the processing operation; g) writing the results to memory for storage and via the memory interface, by way of the obtained memory addresses.