Balanced Binary Tree for Tensor Stream Reducing
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Solution Overview
Problem
Existing deterministic streaming processors face challenges in efficiently implementing stream reducing operations due to complexities in managing dependency between operation completion times in different dimensions, varying delays caused by different aggregation logics, and increased wiring demands.
Innovation Solution
The integration of balanced binary tree structures into the multiplication modules of tensor processors addresses these challenges by canceling out delay dependency in aggregation logic, enabling unified stream reducing operations, and allowing for local optimization of aggregation operations without impacting the overall architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional stream reducing operations are implemented in deterministic streaming processors, then aggregation operations can be performed, but complexity in managing dependency between operation completion times increases
Solution Approach 1:
The patent segments the aggregation operation into two independent phases: data collection phase and aggregation computation phase. This segmentation allows each phase to be optimized independently and eliminates the need to manage dependencies between operations in different dimensions, as each superlane operates autonomously in the collection phase before the centralized aggregation occurs.
Solution Approach 2:
The patent performs preliminary data collection and buffering at each superlane before the actual aggregation computation. By pre-collecting and buffering data in stream registers, the system prepares all necessary inputs in advance, eliminating the need for complex real-time dependency management during the aggregation phase.
2Adaptability or versatility
If different aggregation logics are used for different stream reducing operations, then operation flexibility is improved, but varying delays are introduced
Solution Approach 1:
The patent segments the aggregation process into a collection phase (where different aggregation logics can be applied independently at each superlane) and a computation phase (where standardized processing occurs). This allows flexible aggregation operations with different logics to execute without introducing varying delays, as each superlane operates autonomously in the collection phase.
Solution Approach 2:
The patent allows each superlane to perform partial aggregation operations with different logics as needed, without requiring all superlanes to follow the same aggregation logic. This partial action approach enables operation flexibility while maintaining consistent timing, as each superlane's partial aggregation completes independently before the final computation phase.
3Productivity
If stream reducing operations are implemented with current architecture, then aggregation functionality is achieved, but wiring demands increase
Solution Approach 1:
The patent extracts the aggregation computation function from the data collection path. By separating these functions into distinct phases and locations, the system reduces wiring demands. The collection phase uses simple point-to-point connections, while the aggregation computation phase uses standardized interfaces, eliminating the need for complex wiring to support both functions simultaneously.
Solution Approach 2:
The patent segments the data flow path into collection phase (using stream registers for buffering) and computation phase (using standardized aggregation interfaces). This segmentation allows aggregation functionality to be achieved with reduced wiring demands, as data is collected and buffered locally before being processed through standardized aggregation channels.
Data Source
AI summary
Methods, systems, and other embodiments are described for incorporating a balanced binary tree into the multiplication modules of a tensor processor to execute sequences of instructions more efficiently for Stream Reducing operations. This Abstract and the independent Claims are concise signifiers of embodiments of the claimed inventions. The Abstract does not limit the scope of the claimed inventions.