Daisy Chain Processing Units Reduce Routing Congestion
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Solution Overview
Problem
Conventional parallel processing systems face routing congestion due to shared resource interconnectivity, leading to increased die size and power consumption when attempting to alleviate signal loading through added routing channels and pipeline stages.
Innovation Solution
A multi-processor system configured in a daisy chain architecture, where processing units are connected in a sequence with a demultiplexer and multiplexer to manage packet streams using designated time frames, allowing each unit to read or write data packets during assigned time slots and pass through otherwise, reducing on-chip routing congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple processing elements are arranged in a tandem layout with shared resources, then parallel processing capability is achieved, but routing congestion occurs due to all engines competing for the same shared resources
Solution Approach 1:
The patent segments the shared resource access into multiple dedicated interconnect networks (first interconnect network and second interconnect network). Each network handles specific traffic patterns, dividing the congested routing paths into separate channels. This segmentation eliminates routing congestion while maintaining parallel processing capability by providing dedicated pathways for different data streams.
2Device complexity
If routing channels are added to resolve routing congestion, then signal loading is reduced, but die size increases
Solution Approach 1:
The patent introduces a new dimension to the interconnect architecture by implementing multiple interconnect networks operating in parallel. Instead of adding more channels to a single network (which would increase die size), the solution creates additional network layers/dimensions. Each network handles specific traffic, effectively resolving routing congestion through dimensional expansion rather than lateral expansion, thus avoiding die size increase.
3Speed
If additional pipeline stages are added to reduce signal loading, then operating speed increases, but die size and power consumption increase due to additional logic gates and flip-flops
Solution Approach 1:
The patent introduces dedicated interconnect networks as intermediary structures between processing elements and shared resources. These intermediary networks handle signal routing and loading concerns, allowing the processing elements to operate at higher speeds without directly burdening the shared resources. The intermediary interconnect layers absorb the signal loading effects, enabling high-speed operation without requiring additional pipeline stages that would increase die size and power consumption.
Data Source
AI summary
A processing system includes a group of processing units (“PUs”) arranged in a daisy chain configuration or a sequence capable of parallel processing. The processing system, in one embodiment, includes PUs, a demultiplexer (“demux”), and a multiplexer (“mux”). The PUs are connected or linked in a sequence or a daisy chain configuration wherein a first PU is located at the beginning of the sequence and a last digital PU is located at the end of the sequence. Each PU is configured to read an input data packet from a packet stream during a designated reading time frame. If the time frame is outside of the designated reading time frame, a PU allows a packet stream to pass through. The demux forwards a packet stream to the first digital processing unit. The mux receives a packet steam from the last digital processing unit.