Parallel Memory Banks with Shifted Storage Scheme
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Solution Overview
Problem
Existing memory subsystems for SIMD processors face challenges in efficiently accessing 2D arrays with flexible unaligned data accesses, leading to limited processing throughput and increased silicon area and power dissipation, particularly in video and image processing applications.
Innovation Solution
A one-level memory subsystem with less than N parallel banks and multiple elements per addressable word, combined with a shifted storage scheme, enables parallel access to more than N elements in 1D rows and 2D blocks, optimizing silicon area and power dissipation while supporting flexible access modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional memory subsystems with N parallel banks are used for SIMD processors, then data access capability is provided, but silicon area and power dissipation increase without sufficient processing throughput improvement
Solution Approach 1:
The memory subsystem is segmented into multiple parallel banks (e.g., 8 banks) that can be independently accessed. Each bank handles a portion of the data elements, allowing parallel memory accesses to occur simultaneously across different banks. This segmentation enables the system to service multiple memory requests in parallel without requiring a single large memory array, thus improving processing throughput while controlling silicon area.
Solution Approach 2:
The patent transitions from a single-level memory structure to a multi-dimensional memory organization with multiple banks and multiple elements per addressable word. By adding the dimension of parallel banks and the dimension of multiple elements per word, the system achieves higher effective bandwidth and processing throughput without linearly increasing the total silicon area, as not all memory locations need to be simultaneously accessible.
2Productivity
If traditional memory subsystems with N parallel banks are used for SIMD processors, then data access capability is provided, but power dissipation increases without sufficient processing throughput improvement
Solution Approach 1:
The memory subsystem is segmented into multiple parallel banks (e.g., 8 banks) that can be independently accessed. Each bank handles a portion of the data elements, allowing parallel memory accesses to occur simultaneously across different banks. This segmentation enables the system to service multiple memory requests in parallel without requiring a single large memory array, thus improving processing throughput while controlling silicon area.
Solution Approach 2:
The patent transitions from a single-level memory structure to a multi-dimensional memory organization with multiple banks and multiple elements per addressable word. By adding the dimension of parallel banks and the dimension of multiple elements per word, the system achieves higher effective bandwidth and processing throughput without linearly increasing the total silicon area, as not all memory locations need to be simultaneously accessible.
3Adaptability or versatility
If memory subsystems support flexible unaligned data accesses to 2D arrays, then versatility is improved, but device complexity increases
Solution Approach 1:
The memory subsystem is designed with universal banks that can service multiple types of access patterns through a unified interface. The same bank structure and control logic handle both aligned and unaligned accesses, as well as both 1D and 2D array accesses, without requiring separate dedicated structures for each access type. This multi-functionality achieves versatility while controlling complexity.
Solution Approach 2:
The memory subsystem employs dynamic addressing and control mechanisms that adapt to different access patterns in real-time. The address generation and bank selection logic dynamically adjust based on the specific access requirements (aligned/unaligned, 1D/2D), allowing the system to maintain simplicity in its base structure while achieving flexibility through dynamic operation.
Data Source
AI summary
An electronic apparatus may be provided that includes a processor to perform operations, and a memory subsystem including a plurality of parallel memory banks to store a two-dimensional (2D) array of data using a shifted scheme. Each memory bank may include at least two elements per bank word.