Tagged Interrupt Forwarding for Multiprocessor Cache Efficiency
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Solution Overview
Problem
In multiprocessor systems, cache misses occur during response processing due to data structures not being present in the cache hierarchy of the processor handling the interrupt, leading to decreased system efficiency.
Innovation Solution
A system and method for tagged interrupt forwarding, where the I/O management software prepares a request descriptor with a tag identifying the processor that initiated the request, allowing response processing to be completed at that processor, thereby keeping dynamic and static data structures in its cache hierarchy and avoiding expensive memory accesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If response processing is handled by a different processor than the one that initiated the I/O request, then processor load balancing is improved, but cache miss rate increases
Solution Approach 1:
The patent introduces a tag field in the request descriptor that acts as an intermediary identifier. This tag links the I/O request to its originating processor, enabling the interrupt handler to identify and forward the interrupt to the correct processor. This resolves the contradiction by allowing load-balanced interrupt distribution while maintaining cache locality through processor-specific tagging.
Solution Approach 2:
The patent applies preliminary action by embedding the processor identifier tag in the request descriptor during the initial request phase. This pre-prepared tag enables subsequent interrupt routing decisions without requiring additional lookup or communication overhead, thus maintaining both load balancing and cache efficiency.
2Speed
If data structures are kept in the cache hierarchy during request processing, then request processing speed is improved, but memory usage increases
Solution Approach 1:
The patent applies local quality by maintaining data structures in the cache hierarchy of the specific processor that initiated the I/O request. Rather than requiring all processors to maintain copies of all data structures, each processor keeps only the data structures relevant to its initiated requests, thus improving speed while controlling memory usage through localized caching.
3Productivity
If interrupt handling is distributed across multiple processors, then system throughput is improved, but response processing complexity increases
Solution Approach 1:
The tag field serves as an intermediary that simplifies interrupt routing in distributed processor systems. Instead of requiring complex inter-processor communication or global state tracking, the tag provides a direct identifier that enables each processor to independently determine whether it should handle a given interrupt, thus improving throughput while managing complexity.
Data Source
AI summary
A system for tagged interrupt forwarding comprises a multiprocessor including a first and a second processor, an I/O device, and I/O management software. In response to an application I/O request, the I/O management software may be configured to prepare a request descriptor at the first processor, including an identification of the first processor. The I/O management software may then send a hardware or device-level I/O request to the I/O device. When the I/O device completes the requested hardware I/O operation, it may send a response, which may be received at the second processor. I/O management software at the second processor may be configured to transfer control for processing the response back to the first processor at which the I/O request was initiated, using the tag to identify the first processor. Processing of the response may then be completed at the first processor.