Scalable Micro-Engine Array for SDR Waveform Processing
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Solution Overview
Problem
Current software defined radio (SDR) devices require complex switching matrices for waveform processing, limiting scalability and reconfigurability, as they need multiple layers for each operation and cannot easily add new communication operations without adding new switch layers.
Innovation Solution
A scaleable array processor with interconnected micro-engines in a two-dimensional topology, each with independent local and instruction memory, and FIFOs for intercommunication, allowing flexible reprogramming and configuration without a cumbersome switching matrix, enabling efficient execution of various waveform processing algorithms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a switching matrix is used for waveform processing in SDR devices, then waveform reconfigurability is achieved, but device complexity increases and scalability is limited
Solution Approach 1:
The processing system is divided into multiple independent processing elements (PEs) that can be individually configured and activated. Each PE handles specific waveform processing tasks independently, eliminating the need for a complex centralized switching matrix while maintaining reconfigurability through selective PE activation and interconnection.
Solution Approach 2:
The patent transitions from a two-dimensional switching matrix architecture to a three-dimensional processing element array architecture. This dimensional change allows processing elements to be interconnected in multiple directions (horizontal, vertical, diagonal), providing flexible data flow paths without requiring a complex switching matrix, thus reducing device complexity while maintaining adaptability.
2Adaptability or versatility
If multiple layers of switching matrix are added to support new communication operations, then waveform processing capability is enhanced, but device complexity and manufacturing difficulty increase
Solution Approach 1:
Each processing element is designed as a universal, reconfigurable unit that can perform multiple waveform processing functions. The PEs are interconnected in a standardized array configuration that supports various communication operations without requiring additional layers or complex manufacturing processes. New operations are implemented by reconfiguring existing PEs rather than adding new hardware layers.
3Productivity
If all processing elements operate continuously, then processing throughput is maximized, but power consumption increases
Solution Approach 1:
The processing element array employs dynamic power management where individual PEs are activated or deactivated based on real-time processing requirements. The system can selectively enable only the necessary PEs for current waveform processing tasks, allowing throughput optimization while minimizing power consumption by keeping inactive PEs in low-power states rather than operating all PEs continuously.
Data Source
AI summary
A system for implementing waveform processing in a software defined radio (SDR) includes a scaleable array processor having a plurality of micro-engines (MEs) interconnected by a two dimensional topology. Each micro-engine includes multiple FIFOs for interconnecting to each other in the two dimensional topology. One micro-engine communicates with another adjacent micro-engine by way of the respective FIFOs. The micro-engines are dedicated to predetermined algorithms. The two dimensional topology includes an array of N×M micro-engines interconnected by the multiple FIFOs. The N×M are integer numbers of rows and columns, respectively, in the array of micro-engines. The micro-engines are dedicated to baseband processing of data for RF transmission or RF reception.