Vector Merge Circuitry for Dynamic Lane Allocation in Data Processing
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Solution Overview
Problem
Vector processing units are often underutilized due to limitations in compilers and software developers' failure to utilize vector features, leading to inefficient use of resources in data processing apparatuses.
Innovation Solution
A data processing apparatus with a vector processing unit that includes vector merge circuitry to determine the required number of lanes for processing operations, allowing allocation of execution threads to optimize lane usage and perform operations in parallel, even when fewer lanes are needed, thereby enhancing resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a vector processing unit with M lanes of parallel processing is provided, then processing performance is improved, but device cost increases
Solution Approach 1:
The patent applies partial action by dynamically allocating only the necessary number of lanes (k ≤ M/2) from the vector processing unit to handle groups of execution threads, rather than always utilizing all M lanes. This allows the system to achieve adequate processing performance while avoiding the excessive resource consumption and associated costs of always deploying the full vector processing capacity.
2Productivity
If the vector processing unit executes vector instructions for multiple execution threads, then resource utilization is improved, but the complexity of managing lane allocation increases
Solution Approach 1:
The patent segments the vector processing unit into multiple lanes (M lanes) that can be independently allocated to different execution threads. The vector merge circuitry divides groups of execution threads into smaller subsets, with each subset assigned to a specific number of lanes (k lanes), enabling fine-grained resource management and improved utilization without overwhelming complexity.
Solution Approach 2:
The patent implements dynamic lane allocation where the number of lanes assigned to execution threads is not fixed but adaptively determined by the vector merge circuitry based on the specific instruction requirements and thread group characteristics. This dynamic adjustment optimizes resource utilization while the modular allocation approach keeps management complexity tractable.
3Productivity
If vector merge circuitry allocates execution threads to the vector processing unit, then processing efficiency is improved, but the complexity of the control logic increases
Solution Approach 1:
The vector merge circuitry performs preliminary analysis and allocation of execution threads to the vector processing unit before actual execution. By pre-determining which threads should be grouped together and assigned to k lanes, the system improves processing efficiency through better resource utilization while the allocation decisions are made in advance, reducing the complexity of real-time control logic during execution.
Data Source
AI summary
A data processing apparatus and method are provided for processing execution threads, where each execution thread specifies at least one instruction. The data processing apparatus has a vector processing unit providing a plurality M of lanes of parallel processing, within each lane the vector processing unit being configured to perform a processing operation on a data element input to that lane for each of one or more input operands. A vector instruction is received that is specified by a group of the execution threads, that vector instruction identifying an associated processing operation and also providing an indication of the data elements of each input operand that are to be subjected to that associated processing operation. Vector merge circuitry then determines, based on that information, a required number of lanes of parallel processing for performing the associated processing operation. If it is determined that the required number of lanes is less than or equal to half the available number of lanes within the vector processing unit, then the vector merge circuitry allocates a plurality of the execution threads of the group to the vector processing unit such that each execution thread in that plurality is allocated different lanes amongst the available lanes of parallel processing. As a result, the vector processing unit then performs the associated processing operation in parallel for each of the plurality of execution threads, significantly increasing performance.