Super-Descriptor Engine Chaining in SoC Storage Controllers
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Solution Overview
Problem
Current RAID-on-chip (RoC) and storage controller architectures lack efficiency in data flow management, requiring frequent firmware intervention and not utilizing hardware queues and shared memory effectively, leading to suboptimal performance and inflexibility in supporting advanced data security and RAID functions.
Innovation Solution
The introduction of a Super-Descriptor data flow method that chains multiple engines within a System on Chip (SoC) controller, utilizing a centralized shared memory and queuing system to enable efficient data operations without firmware intervention, allowing for flexible configuration and improved throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional RAID-on-chip architecture is used with frequent firmware intervention, then system reliability is maintained through centralized control, but productivity and performance are reduced due to firmware overhead
Solution Approach 1:
The patent segments the data flow processing by introducing multiple independent engines (DMA engine, RAID engine, encryption engine, compression engine) that can operate autonomously in parallel. Each engine handles specific tasks without requiring centralized firmware coordination, thereby increasing productivity while reducing firmware overhead.
Solution Approach 2:
The patent implements self-service mechanisms where engines automatically pass descriptors to each other through shared memory queues without firmware intervention. The DMA engine completes transfers and automatically posts completion descriptors to the RAID engine queue, which then processes and passes to subsequent engines, creating a self-sustaining data flow pipeline.
2Adaptability or versatility
If multiple engines are chained with super-descriptor execution, then adaptability for advanced RAID and security functions is improved, but device complexity increases due to additional hardware components
Solution Approach 1:
The patent creates a universal engine chain architecture where a standardized sequence of engines (DMA, RAID, encryption, compression) can handle multiple different data flow types. The same engine infrastructure supports various RAID levels, encryption algorithms, and compression methods through configurable descriptors rather than dedicated hardware for each function.
Solution Approach 2:
The patent implements nested functionality where descriptors are embedded within super-descriptors, and engines are nested in a processing chain. The super-descriptor contains multiple descriptors that are executed sequentially by different engines, allowing complex operations to be composed of simpler nested components.
3Loss of time
If engines execute super-descriptors without firmware intervention, then loss of time is reduced through continuous operation, but measurement precision and control are worsened due to reduced firmware oversight
Solution Approach 1:
The patent implements feedback mechanisms where each engine monitors its own execution status and automatically posts completion descriptors to the next engine's queue. The DMA engine provides feedback on transfer completion, the RAID engine provides feedback on parity calculation status, and so on, creating a self-regulating system that maintains precision without firmware intervention.
Solution Approach 2:
The patent introduces shared memory queues as intermediaries between engines. These queues serve as mediators that precisely track the state of data flow between engines, allowing the system to maintain measurement precision through the intermediary structures rather than requiring direct firmware monitoring of each engine transition.
Data Source
AI summary
A method of chaining a plurality of engines for a system on chip (SOC) controller device and a SOC controller device are disclosed herein. The method comprises: generating, at an initiator, a super-descriptor for providing instructions to the plurality of engines of the SOC controller; passing the super-descriptor from the initiator to a first engine of the plurality of engines; and executing a portion of the super-descriptor at each of the plurality of engines in series without the intervention of the initiator.