Parallel Processor Dynamic Addressing for Non-Homogeneous Zones

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Solution Overview

Problem

Conventional SIMD parallel processors face difficulties in efficiently processing operations where pixels as operands and results span non-homogeneous address zones, leading to complex programming and reduced execution efficiency, especially in image processing and signal processing applications.

Innovation Solution

The solution involves defining the set of reads and writes for each elementary processor as a field of action within a unique data structure, allowing each processor to calculate its own addresses based on the position of the field of action and its position in the topology, enabling flexible handling of non-homogeneous address zones.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional SIMD processors use fixed address zones for each processor, then address calculation is simple, but processing of non-homogeneous address zones becomes complex and inefficient

Engineering Contradiction:
Improveexecution efficiencyVSAvoidprogramming complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces dynamic address calculation where each processor computes its operand and result addresses based on the field of action position and its own position in the topology. This dynamic approach replaces fixed address zones, enabling efficient processing of non-homogeneous address zones while maintaining systematic address management through the formulas: operand address = Int((Wmin+Np-1-p)/Np) and result address = Int((Emin+Np-1-p)/Np)

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the addressing parameter from fixed zone assignment to dynamic calculation based on field of action boundaries (Wmin, Emin) and processor position (p). This parameter transformation allows the system to adapt to non-homogeneous address zones while maintaining efficient parallel execution across all processors

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If processors access data across non-homogeneous address zones, then flexibility in data access is improved, but address calculation complexity increases

Engineering Contradiction:
Improveaddress zone flexibilityVSAvoidaddress calculation complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent transforms the addressing system by introducing field of action boundaries (Wmin, Emin) as key parameters. Each processor calculates addresses using these parameters along with its position, enabling flexible access across non-homogeneous zones. The address calculation formulas Int((Wmin+Np-1-p)/Np) and Int((Emin+Np-1-p)/Np) provide systematic computation that maintains adaptability while controlling complexity through mathematical regularity

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

Each processor independently calculates its own operand and result addresses using the field of action position and its own position in the topology. This self-service approach eliminates the need for centralized address assignment, allowing processors to autonomously handle non-homogeneous address zones while reducing overall system complexity

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10789072B2Parallel processor for calculating operand and result addresses as a function of a position of a field of action and predetermined positions of processing elements in non-homogeneous address zones within a topology
Publication Date: 2020.09.29 THALES SA
  • US10789072B2 patent drawing
  • US10789072B2 patent drawing
  • US10789072B2 patent drawing

AI summary

A parallel processor comprising elementary processors disposed according to a topology with a predetermined position within this topology and capable of simultaneously executing the same instruction on different data, the instruction relating to at least one operand and/or providing at least one result The instruction comprises, for each operand and/or each result, information relating to the position of a field of action within a table data structure of dimension N type, and the parallel processor calculates the address of each operand and calculates the address of each result within each elementary processor, as a function of the position of the field of action and of the position of the elementary processor within the topology.