PLD Logic Circuit Replacement Based on Save and Restore Time
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Solution Overview
Problem
In programmable logic devices (PLDs), when the number of logic circuits exceeds the available circuit resources, existing technologies face inefficiencies in dynamically reconfiguring and replacing circuits to manage multiple tasks efficiently, leading to suboptimal processing and resource utilization.
Innovation Solution
A control program for PLDs that identifies and replaces logic circuits based on save and restore time, selecting circuits with shorter save and restore times to efficiently manage reconfiguration and resource allocation, ensuring continuous operation and high-speed task execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple logic circuits are configured in a PLD to execute multiple tasks, then task processing capability is improved, but when the number of logic circuits exceeds circuit resources, inefficient time-sharing and resource utilization occur
Solution Approach 1:
The patent changes the parameter of logic circuit replacement by introducing a new selection criterion based on save and restore time. Instead of arbitrary or simple FIFO replacement, the system dynamically selects which logic circuit to replace by evaluating the time required to save its state data and restore it later, thereby optimizing resource management efficiency
Solution Approach 2:
The control circuit automatically manages the replacement of logic circuits by autonomously evaluating save and restore times and making replacement decisions without external intervention. This self-service mechanism optimizes resource utilization by continuously monitoring and managing circuit resources based on actual operational characteristics
2Adaptability or versatility
If logic circuits are replaced dynamically to manage multiple tasks, then resource utilization is improved, but save and restore time becomes a critical factor affecting execution speed
Solution Approach 1:
The system performs preliminary evaluation of save and restore times before making replacement decisions. By pre-assessing the time cost of saving and restoring state data for each logic circuit, the control circuit can predict the impact of replacement on execution speed and select the optimal target, thereby minimizing time loss during dynamic reconfiguration
3Ease of operation
If existing replacement methods are used when logic circuits exceed available resources, then basic time-sharing is achieved, but processing efficiency and resource utilization become suboptimal
Solution Approach 1:
The patent implements a feedback mechanism where the control circuit continuously monitors the save and restore times of logic circuits and uses this information to make informed replacement decisions. This feedback loop ensures that replacement strategies are dynamically adjusted based on actual performance characteristics, thereby optimizing both ease of operation and processing efficiency simultaneously
Data Source
AI summary
A PLD control program causes a computer to execute process including: outputting a configuration request for configuring a logic circuit in any of a plurality of areas where logic circuits are enabled to be reconfigured in a programmable logic device (hereinafter referred to as a PLD); and selecting, when a total size or number of a plurality of first logic circuits already configured in the plurality of areas and a second logic circuit newly configured in accordance with the configuration request exceeds a size or a number of logic circuits that are enabled to be configured in the plurality of areas, a logic circuit to be replaced with the second logic circuit, as a replacement target, from among the plurality of first logic circuits, based on a save and restore time needed to save and restore state data in the first logic circuits.