Configurable Multi-Core Image Processor with Dynamic Internal Network
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Solution Overview
Problem
Traditional image processors either consume high energy due to versatile software development capabilities or are limited in tasks due to fixed function hardwired circuitry, lacking a balance between versatility and power efficiency.
Innovation Solution
A processor with multiple cores and an internal network that can be configured to enable a variable number of cores to be communicatively coupled, allowing for both versatile application software development and improved power efficiency by dynamically adjusting core usage based on the specific software requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If general purpose processor with vector instruction enhancements is used, then versatile application software development platform is provided, but energy consumption per unit of data increases
Solution Approach 1:
The processor is divided into multiple independent cores (e.g., 8 cores) that can be selectively activated. Each core can be independently controlled, allowing the system to segment the processing workload and activate only the necessary number of cores for each specific task, thereby reducing overall energy consumption while maintaining versatility.
Solution Approach 2:
The processor implements dynamic configuration capability where the number of active cores can be changed at runtime based on software requirements. The system can transition between different operational states (e.g., 1 core, 2 cores, 4 cores, or 8 cores active), allowing optimal energy-performance trade-offs for different application scenarios.
2Use of energy by moving object
If fixed function hardwired circuitry is used, then power consumption per unit of data is reduced, but the set of performable tasks is limited
Solution Approach 1:
The processor cores are designed with universal functionality, capable of executing various types of processing tasks through software configuration rather than hardwired functions. Each core can be programmed to perform different operations (e.g., image processing, video encoding, neural network inference), providing multi-functionality without requiring separate fixed-function circuits for each task.
Solution Approach 2:
The processor allows dynamic change of operational parameters including the number of active cores, clock frequency, and voltage levels. By adjusting these parameters based on task requirements, the system can optimize power consumption for different workloads while maintaining the ability to perform diverse tasks through software reconfiguration.
3Adaptability or versatility
If all cores are activated for versatile task processing, then task flexibility is maintained, but power consumption increases
Solution Approach 1:
The system implements partial action by activating only the necessary subset of cores required for each specific task rather than always running all cores. For example, a simple task may only require 1 or 2 cores to be active, while more complex tasks can utilize 4 or 8 cores, avoiding the excessive energy consumption of always maintaining full processor capacity.
Solution Approach 2:
The processor includes feedback mechanisms that monitor task requirements and dynamically adjust the number of active cores accordingly. The system can detect when fewer cores are sufficient for the current workload and reduce active core count to save power, while automatically scaling up when task complexity increases, thus optimizing the balance between flexibility and power consumption.
Data Source
AI summary
A method is described. The method includes configuring a first instance of object code to execute on a processor. The processor has multiple cores and an internal network. The internal network is configured in a first configuration that enables a first number of the cores to be communicatively coupled. The method also includes configuring a second instance of the object code to execute on a second instance of the processor. A respective internal network of the second instance of the processor is configured in a second configuration that enables a different number of cores to be communicatively coupled, wherein, same positioned cores on the processor and the second instance of the processor have same network addresses for the first and second configurations. A processor is also described having an internal network designed to enable the above method.