Reconfigurable Processor Mini-Cores Loop Scheduling

The patent divides the array processing units into multiple independent mini-cores, where each mini-core is a self-contained processing unit capable of executing loop iterations independently. This segmentation allows each mini-core to be scheduled separately, enabling efficient utilization even when the total number of function units is large. The local scheduler within each mini-core manages its own function units, avoiding the scheduling complexity that arises in conventional approaches when scaling up the number of function units.

The patent introduces a global scheduler that performs preliminary scheduling of loop iterations across multiple mini-cores before execution. The global scheduler analyzes dependency relationships between loop iterations and assigns them to appropriate mini-cores in advance, determining the optimal start time for each iteration. This preliminary action enables loop iterations with dependencies to be executed in parallel across different mini-cores rather than sequentially, maintaining dependency constraint satisfaction while significantly improving processing speed through parallel execution.