Stream Data Processor Architecture for Wireless Baseband Efficiency
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Solution Overview
Problem
Existing digital baseband integrated circuits for wireless communications face challenges in flexibility, die size, and power efficiency, with dedicated hardware offering the best efficiency but lacking a straightforward migration path from flexible to efficient solutions, while software-defined radio implementations provide flexibility but not die size and power efficiency.
Innovation Solution
A stream data processor (SDP) architecture is used, partitioning each SDP into Stream Processor Units (SPUs) for dedicated hardware processing and a Stream Control Unit (SCU) for configuration, allowing optimized operand widths and flexible sequencing, enabling efficient data processing and configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If dedicated hardware designs are used, then die size and power efficiency are improved, but flexibility and adaptability deteriorate
Solution Approach 1:
The patent implements a reconfigurable data processing unit that can dynamically change its operational mode between scalar processing, SIMD processing, and VLIW processing. This dynamic reconfigurability allows the system to adapt its architecture to match the specific requirements of different algorithms, thereby maintaining flexibility while achieving dedicated-hardware-level efficiency for specific tasks.
Solution Approach 2:
The reconfigurable data processing unit is designed to perform multiple functions: it can operate as a scalar processor, an SIMD processor, or a VLIW processor. This multi-functionality allows a single hardware unit to replace multiple dedicated hardware designs, providing both the flexibility of software-defined radio and the efficiency of dedicated hardware.
2Adaptability or versatility
If software-defined radio implementations are used, then flexibility is improved, but die size and power consumption worsen
Solution Approach 1:
The system uses a reconfigurable data processing unit that can dynamically adjust its operational mode (scalar, SIMD, or VLIW) based on the algorithm being executed. This dynamic adaptation allows the system to achieve dedicated-hardware-level compactness and efficiency for specific tasks while retaining the flexibility to reconfigure for different algorithms.
Solution Approach 2:
The patent changes the operational parameters of the data processing unit by switching between different execution modes (scalar, SIMD, VLIW). This parameter change allows the same hardware to achieve different levels of parallelism and efficiency, optimizing both die size utilization and processing performance for different algorithms.
3Productivity
If reconfigurable data processing units with high parallelism are used, then processing power is improved, but control complexity and difficulty of software tool implementation worsen
Solution Approach 1:
The reconfigurable data processing unit dynamically switches between scalar, SIMD, and VLIW modes based on the algorithm requirements. This dynamic approach simplifies control by selecting the most appropriate execution mode rather than managing complex reconfiguration for each operation, reducing software tool complexity while maintaining high processing power when needed.
Solution Approach 2:
The system provides three levels of parallelism (scalar, SIMD, VLIW) that cover most processing needs. By offering a stepped approach rather than full reconfigurability for every possible operation, the system achieves high processing power for parallel algorithms while keeping control complexity manageable through a limited set of well-defined execution modes.
Data Source
AI summary
Techniques are provided aimed at improving the flexibility and reducing the area and power consumption of digital baseband integrated circuits by using stream data processor based modem architecture. Semiconductor companies offering baseband ICs for handsets, face the challenges of improving die size efficiency, power efficiency, performance, time to market, and coping with evolving standards. Software defined radio based implementations offer a fast time to market. Dedicated hardware designs give the best die size and power efficiency. To combine the advantages of dedicated hardware with the advantages of conventional software defined radio solutions the stream data processor is partitioned into a stream processor unit, which implements processing functions in dedicated hardware and is hence die size and power efficient, and a flexible stream control unit which may be software defined to minimize the time to market of the product.