Ambipolar 2D Floating-Gate Logic for Reconfigurable Transistors
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Solution Overview
Problem
Conventional reconfigurable transistors are complex due to multiple gate terminals, limiting integration density and efficiency, and three-dimensional transistor integration is hindered by heat generation and vertical layer stacking limitations.
Innovation Solution
A reconfigurable electronic device using an ambipolar two-dimensional semiconductor with a control gate, floating gate, tunneling layer, and channel layer, allowing charge type and concentration adjustment via program voltage, and a logic device composed of multiple such devices for enhanced integration and operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional reconfigurable transistors use multiple gate terminals to achieve reconfigurability, then operational flexibility is improved, but device complexity increases and integration density decreases
Solution Approach 1:
The patent implements a single gate terminal that can perform multiple functions by adjusting its electrical characteristics. The gate electrode serves as both a control gate for transistor operation and a programming electrode for memory functionality, eliminating the need for separate gate terminals while achieving reconfigurability between different operational modes (transistor switch, memory cell, logic gate)
Solution Approach 2:
The patent merges the control gate and floating gate into a single gate electrode structure. This unified gate terminal combines the functions of conventional multi-gate transistors into one component, simplifying the circuit configuration while maintaining the ability to perform various logical operations through electrical characteristic adjustment
2Quantity of substance
If three-dimensional integrated circuits stack electronic devices vertically to increase integration density, then device integration density is improved, but heat generation increases and vertical layer stacking is limited
Solution Approach 1:
The patent merges memory and transistor functions into a single reconfigurable device, reducing the number of separate vertical layers needed in 3D integration. This consolidation decreases the overall vertical stack height and reduces heat generation from multiple independent devices, while maintaining high integration density through the multi-functional nature of each device
3Quantity of substance
If silicon semiconductor transistors are miniaturized to increase device integration density, then device integration density is improved, but short-channel effects increase and physical limits are reached
Solution Approach 1:
The patent changes the material parameter from conventional silicon semiconductor to two-dimensional semiconductor material (such as MoS2, WSe2, or black phosphorus). This material substitution enables effective suppression of short-channel effects even at miniaturized dimensions while maintaining high device integration density, as the two-dimensional nature of these materials provides superior electrostatic control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device achieves efficient memory and transistor functions with high charge mobility, suppresses short-channel effects, and performs various logical operations, enhancing integration density and operational flexibility.
Implementation Method 1
a tunneling layer that is formed on the floating gate
Data Source
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AI summary
A reconfigurable electronic device that may perform various operations by adjusting the type and concentration of a charge stored in a floating gate, and a manufacturing method thereof and a logic device using thereof, are provided. Such reconfigurable electronic device comprises a control gate; a floating gate that is formed on the control gate and that is electrically insulated from surroundings; a tunnelling layer that is formed on the floating gate; a channel layer that is formed on the tunnelling layer and that is composed of the ambipolar two-dimensional semiconductor; and a first electrode and a second electrode, that are formed on the channel layer to be spaced apart from each other. Here, the channel layer has any one characteristics of a conductor, an n-type semiconductor, an insulator and a p-type semiconductor depending on the polarity and magnitude of a program voltage applied to the control gate.